Synopsys has added a Performance Checker capability to their next-generation Discovery Verification IP (VIP) for the ARM AMBA 4 AXI4 protocol. The Performance Checker capability in the Synopsys Discovery VIP helps improve the productivity of engineering teams using the AMBA protocols to meet their SoC performance goals.
The Performance Checker capability enables system-on-chip (SoC) verification engineers to analyze and validate SoC performance using metrics established during the system architecture definition process, speeding up the debug of SoC performance bottlenecks. The Performance Checker capability in Synopsys’ Discovery VIP for AMBA 4 AXI4 leverages the investment made in optimizing the system architecture to SoC verification, accelerating the overall verification process.
The Performance Checker capability builds on Discovery VIP data integrity checking to track latencies across an AMBA 4 AXI4 or ACE interconnect. Metrics defined in Synopsys’ Platform Architect during architecture exploration are passed to the Discovery VIP as constraints to ensure consistency of system-performance through the design flow.
The Performance Checker capability enables the Discovery VIP to identify performance violations and generates reports that help users validate their implementation against the optimized system’s performance goals, with a substantially wider range of real-life traffic. In addition, violations are highlighted in Synopsys’ Protocol Analyzer protocol-aware debug environment to simplify debug and accelerate root-cause analysis.
More info: Synopsys Discovery Verification Platform