Forte Design Systems Launches New Version of Cynthesizer SystemC High-level Synthesis

Cynthesizer SystemC high-level synthesis (HLS) ~ Forte Design Systems

Forte Design Systems launched a new version of Cynthesizer SystemC high-level synthesis (HLS). Cynthesizer v4.3 features improvements in power results and ease of use while expanding their CynWare IP library. This enables design teams to quickly adopt high-level synthesis. New features include new modeling style support, expanded optimization and analysis capabilities, integration with third-party tools and improvements to CynWare intellectual property (IP) cores. Version 4.3 of Forte Cynthesizer is shipping now.

New Cynthesizer 4.3 Features

  • Supports the synthesis of the standard C++ math library “<complex>” in addition to the CynWare fixed point data types. This modeling technique maintains precision throughout complex computations in the high-level SystemC design and creates optimized RTL code through the HLS process. Cynthesizer 4.3 adds support for asynchronous zero-latency memories in addition to the extensive memory capabilities built into the product.

  • The use of C++ templates and virtual functions has been expanded for defining module structure and behavior to allow users to express design intent at a higher level, reducing the amount of code required and increasing reusability. Cynthesizer supports the use of the standard math libraries with C/C++ and SystemC datatypes.

  • Cynthesizer Workbench (CynthWB) environment enhancements include formatting and filtering of tabular reports and the ability to link objects to the call stack to improve debugging and optimizing of the design. Support has been added for asynchronous external memories, along with variable accesses to arrays of external memories, register banks and memories to support more design styles and provide better results. Large projects will load quickly in CynthWB and navigation through analysis data is faster. The layout for analyzing synthesis results has been improved, and an analysis capability that compares quality of results (QoR) of two selected cynthConfigs is included.

  • Forte’s CynWare IP library and CynWare Interface Generator have been updated to improve quality of results and usability. In a power saving move, the CynWare Line Buffer IP interface now allows memory reads to be avoided for unneeded rows or columns. To improve performance and prevent avoidable pipeline stalls, CynWare FIFOs implemented with single-ported memories have an extra buffer register to decouple the synthesized design from the FIFOs internal read-write cadence.

  • Cynthesizer integrates with the Cadence Incisive Enterprise Simulator and the SimVision debugging environment, and Oasys Design Systems’ RealTime Designer to link high-level synthesis to chip synthesis.

  • The tools supports mapping arrays in a design to either a flattened set of registers or a memory, and maps arrays to a register bank for improved capacity and runtime. Designs with large register banks can be mapped directly to a register bank instead of flattening the array.

More info: Forte Design Systems