Cadence Design Systems released version 16.6 of their Allegro Package Designer and System-in-Package (SiP) Layout solution. Allegro now enables engineers to analyze and validate high-performance, low-power devices for electrical compliance. This improves design time and speeds time to market. New enhancements in Cadence Allegro enable a more predictable and efficient design cycle. Cadence Allegro release 16.6 IC package solution is expected to be available in the fourth quarter of this year.
Allegro v16.6 supports low-profile IC package requirements for next-generation smartphones, tablets, and ultra-thin notebook PCs. The tool features open cavity support for die placement, a new wirebond application mode that improves efficiency, and a wafer-level-chip-scale-package (WLCSP) capability that delivers the industry’s most comprehensive design and analysis solution for IC package design.
Allegro tools include built-in functionality for addressing the challenges associated with IC package implementation for small and thin consumer electronics products. The Allegro v16.6 solution supports a new database object for open cavity placement that provides enhanced capabilities, such as DRC and 3-D viewing, to support die placement within a cavity of the package substrate. A new intuitive wirebond application mode improves throughput by focusing specifically on the wirebond process.
The Cadence Allegro suite enables a highly efficient WLCSP flow by reading and writing more concise GDSII data. A new advanced package router, based on Sigrity technology, significantly accelerates the substrate-level interconnect implementation of a package. In addition, package assessment, model extraction, signal and power integrity analysis have been integrated into the Allegro 16.6 tool. This makes the analysis and signoff portion of the IC package design flow much easier and quicker.
Allegro Package Designer and Cadence SiP Highlights
- New wirebond application mode reduces menu picks and accelerates design creation
- New Open Cavity database object enables placement of die below the substrate surface, allowing you to create low-profile IC packages
- Wafer-level chip-scale-package (WLCSP) flow enhanced through GDSII in/out improvements
- New option for integrated Advanced Package Router (Sigrity technology)
- New options for integrated signal integrity and power integrity signoff flows (Sigrity technology)
More info: Cadence IC Packaging and SiP 16.6