Synopsys Galaxy Implementation Platform Supports TSMC 20nm Process

Synopsys is offering 20nm process technology support for the TSMC 20nm Reference flow. The 20nm process offers measurable power, performance and area benefits. TSMC and Synopsys have collaborated closely from the very early stages of 20 nanometer process development to address the challenges of 20nm design. The results of this collaboration will help designers maximize the benefits of the 20nm process to deliver the designs predictably and on time.

TSMC’s 20nm Reference Flow addresses 20nm design challenges with a transparent double patterning aware design flow enabling double patterning technology (DPT) compliance, pre-coloring capability, new RC extraction methodology, DPT sign-off, and integrated design-for-manufacturing (DFM). The new Reference Flow’s transparent DPT enablement reduces DPT design complexity, achieves required accuracy, minimizes 20nm design flow setup and learning curve, and accelerates 20nm process adoption.

Synopsys Galaxy Implementation Platform now supports the latest TSMC 20nm design rules and models. The collaboration between TSMC and Synopsys on 20nm technology enables engineers to gain performance, power efficiency and chip density advantages while achieving predictable design closure with the industry-proven Synopsys RTL to GDSII solution.

Synopsys’ Galaxy Implementation Platform Support for TSMC 20nm Process Highlights

  • IC Compiler
    Offers industry’s leading solution for power, performance and area on advanced node designs, and enables designers to create DPT compliant layout that can be reliably decomposed during manufacturing
  • IC Validator
    Features a fast, accurate decomposition (coloring engine) to perform double-patterning checks during design, and can also perform automatic fixing of violations with IC Compiler via In-Design technology
  • PrimeTime
    Enables double-patterning-aware variation analysis that includes multi-valued SPEF model variation and its impact on timing
  • StarRC
    Provides silicon-calibrated modeling to account for mask misalignment due to double patterning and non-color and color-aware extraction for accurate, high-performance design

More info: Synopsys, Inc.

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