Cadence Incisive Debug Analyzer Reduces Debug Time by 40%

Cadence Design Systems launched the Incisive Debug Analyzer. The new tool is a verification debug solution for RTL, testbench and SoC verification. It helps designers reduce debug time and effort. The Incisive Debug Analyzer integrates seamlessly into existing Incisive debug flows, fully leveraging SimVision for waveform and transaction-level debug. The tool will be released at the end of the year.

Cadence Incisive Debug Analyzer features integrated, interactive log file analysis capabilities with smart filtering and clickable messages that take engineers directly to the point of interest in either the source code or the waveform database. The debugger provides relevant debug investigation information that allows designers to quickly and easily filter messages coming from any platform (HVL and HDL code) and explore the cause of the messages by providing causality relations and debugging leads.

According to Cadence, many SoC companies now spend over 50% of their overall verification effort in debug. Incisive Debug Analyzer targets this verification bottleneck with unique debug features. For instance, the debugger enables designers to step forward or backward through their hardware verification language (HVL) and hardware description language (HDL). In addition, designers can click directly on a line or variable to jump forward or backward through time to the point when the source code line was executed or a variable value changed, allowing them to pinpoint the bug(s).

More info: Cadence Design Systems, Inc.