Cadence Design Systems is holding a Low-Power Technology Summit. The event will be keynoted by UC Berkeley Professor Jan M. Rabaey. He is the author of Low Power Design Essentials (Integrated Circuits and Systems). Rabaey will address power issues that impact today’s chip designers. The one-day technical conference will take place on October 18th at Cadence Design Systems in San Jose, California. The event is free.
The Low-Power Technology Summit also features presentations like “Low-Power Design with ARM Physical IP and POP IP” (Sathya Subramanian of ARM) and “Low-Power Design Experiences on Freescale Kinetis MCU Family” (Anis Jarrar of Freescale). In addition, Dr. Qi Wang of Cadence will deliver an update on power format standards. There will also be an afternoon panel discussion on low-power techniques.
Low-Power Technology Summit Topics
- Low-Power Solution Technology Update
- Low-Power Design with ARM Physical IP and POP IP
- Low Power Verification in Mixed-Signal Designs
- Cadence Technology and Customer Experiences
- Customer Case Study: Low-Power Design Experiences on Kinetis
- Power Formats: Standards and Support Update
- R&D Roundtable
- Panel Discussion and Q&A
Register: Low-Power Technology Summit