Cadence Design Systems introduced version 16.6 of the OrCAD PCB tool. The design solution includes new features, enhanced customization capabilities, and 20% simulation performance improvements to help engineers with product creation. The new version offers improved usability, performance and productivity. The Cadence OrCAD v16.6 PCB design solution is expected to be available in the fourth of this year.
Cadence OrCAD v16.6 PCB design solution features a new signal-integrity flow with a higher level of automation that gives usability and productivity benefits for circuit simulation of performance-driven digital circuits requiring pre-layout topology and constraint exploration and development for high-speed design. The expanded/new signal-integrity flow provides a seamless, bidirectional interface between the OrCAD Capture and the OrCAD PCB SI tools. This new integration enables an automated and comprehensive design methodology that streamlines pre-layout topology and constraint exploration improving productivity by 100%.
OrCAD 16.6 PSpice improves user productivity by providing simulation convergence improvements and an average 20% gain in simulation speed. The gains are achieved through the introduction of multi-core support for simulations involving large designs and designs dominated by complex models such as MOSFETs and BJTs.
OrCAD v16.6 extends the Tcl programming capability and apps methodology from OrCAD Capture to PSpice. As a result, designers can extend and customize their simulations and environment beyond what is possible with a standard ‘out-of-box’ solution. With Tcl access to the simulation data and environment, engineers may customize simulations with tolerances on any parameter, map user parameters, or program PSpice with user-defined equations and expressions.
More info: Cadence OrCAD 16.6 Release