ProPlus Design Solutions launched NanoYield design for yield software. It is a fast and accurate yield prediction and optimization tool for memory, logic, analog and digital circuit design. The toolset is faster than traditional Monte Carlo analysis for both regular three-sigma and advanced six-sigma analysis. NanoYield is part of ProPlus Design Solutions’ transistor-level statistical modeling and design and variations-aware product portfolio. It is shipping now.
NanoYield features High Sigma analysis, advanced Monte Carlo analysis and NanoSPICE parallel SPICE simulator to accelerate statistical simulation performance. The tool can be integrated into an existing design flow and predicts yield at early design stages. It helps engineers to evaluate and optimize integrated circuit (IC) designs for optimum yield and performance tradeoffs.
NanoYield features algorithms and parallel technologies for accelerating statistical simulation performance. The tool’s engine is the NanoSpice parallel SPICE simulator and contains Monte Carlo Pro (MC-Pro) technology with parallel processing that can deliver 10 to 100 times acceleration over traditional Monte Carlo products. Its High Sigma Pro (HS-Pro) feature licensed and validated by IBM increases high-sigma (e.g., 5-6s) statistical simulation performance by 103 to 106 times, offering accurate predictions of the extreme low-failure rate of cell blocks. With HS-Pro, engineers can predict the yield of repetitive structure circuits, such as memory where small cell failure rate is necessary but not predictable by practical Monte Carlo runs.
NanoYield Design-for-Yield Toolset Features
- Innovative parallel statistical simulation engine for yield prediction and design optimization
- MCA technology with full sampling delivers 6-10X speedup over traditional Monte Carlo
- MCP technology adopts advanced sampling methods and boosts statistical simulation performance by additional 3-10X
- Unique MCFastCell technology can further improve the statistical simulation performance for small-size cells
- HSP technology for the DFY design of circuits with repetitive structures
- Accurate prediction of the extremely low failure rate of cell blocks
- Validated for memory, sensitive digital/ASIC circuits, etc.
- Sensitivity analysis, dependence analysis, High Sigma analysis, etc.
- Significant speed-up over traditional methods by hundreds to millions of times
- Industry standard input/output
- Fully compatible with HSPICE/Spectre format inputs
- Rich circuit analysis functions
- Supporting industry standard device models
- Integration with Cadence Virtuoso Analog Design Environment
- Supporting Cadence IC 5141 and IC 61x
- Rich statistical analysis functions
- Supporting 64bit multi-core system
- RedHat RHEL 4.x, 5.x
More info: NanoYield Design-for-Yield (DFY) Toolset