Tanner HiPer Silicon v15.23 Features HiPer Simulation AFS and T-AFS

Tanner EDA's S-Edit design environment for schematic capture

Tanner EDA introduced the latest version of HiPer Silicon full-flow analog and mixed-signal design suite. HiPer Silicon v15.23 includes HiPer Simulation AFS and Tanner Analog FastSPICE (T-AFS), which integrates the Berkeley Design Automation Analog FastSPICE Platform with Tanner EDA’s S-Edit schematic capture and W-Edit waveform analyzer.

HiPer Silicon version 15.23 gives designers added capabilities for front-end design flow, including schematic capture, dual circuit simulators and waveform probing. According to Tanner EDA, the company now offers the fastest, most productive and robust front end analog design package on the market. Developers can now verify complex analog and RF circuits with nanometer Spice accuracy while still taking advantage of Tanner EDA’s industry-leading price-performance.

With HiPer Simulation AFS, two Spice simulators increases performance and productivity, even for large netlists. T-Spice provides fast, accurate analysis while T-AFS delivers accuracy with runtimes 5x to 10x faster than traditional Spice simulators, on a single core. Engineers can drive the T-AFS simulator directly from S-Edit, getting the speeds and accuracy necessary for nanometer design. Simulation results are displayed automatically in W-Edit for viewing, measuring, and analyzing interactively.

HiPer Silicon v15.23 also adds new TCL commands to S-Edit, supporting greater functionality. In addition, T-Spice now supports the HiSIM-HV model. Integration with Berkeley Design Automation transient noise analysis capability enables designers to simulate realistic device noise effects for all circuits, especially non-periodic circuits such as sigma-delta ADCs and frac-N PLLs.

More info: Tanner HiPer Simulation AFS