ASSET InterTech Publishes IJTAG Tutorial on New Standard for Chip Validation and Characterization

ASSET InterTech IJTAG Tutorial

ASSET InterTech has published an introductory tutorial on IJTAG. The tutorial explains how the new IEEE P1687 Internal JTAG (IJTAG) standard simplifies and automates the way chip designers manage embedded instruments that perform chip validation and characterization. The article describes the on-chip IJTAG architecture and the two languages defined by the standard, Instrument Connectivity Language (ICL) and Procedural Description Language (PDL). ICL defines the connections among embedded on-chip instruments and PDL is an extension of the Tcl (Tool Command Language) for developing validation, test and debug vectors for execution by IJTAG instruments.

The IJTAG standard specifies a standard interface to instruments embedded in chips, and defines a methodology for accessing them, automating their operations and analyzing their outputs. To allow for a wide variety of functionality, an instrument’s core intellectual property (IP) does not need to conform to the IJTAG standard, just the instrument’s interface to the on-chip IJTAG network. With standardized embedded instrumentation chip designers are better able to manage the hundreds or thousands of instruments that are typically embedded in complex components and systems-on-a-chip (SoC). The standard defines an architecture that can automatically connect all IJTAG instruments as well as an access methodology for automating their operations.

IJTAG Tutorial

The goal of IEEE P1687 Internal JTAG (IJTAG) is to streamline the use of instruments that have been embedded in chips. The intent is to facilitate the deployment of these embedded instruments in a wider array of chip, board and system level validation, test and debug applications. Over the last decade, semiconductor manufacturers have embedded instruments in their chips to simplify the characterization, testing and debugging of these devices. Given the right standards-based tools environment, these same instruments can perform a much broader spectrum of chip, board and system level validation, test and debug applications.

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