Cadence Encounter Digital Platform Optimizes ARM POP IP

ARM and Cadence Design Systems teamed together to create a solution that uses the Cadence Encounter digital platform to optimize ARM POP intellectual property (IP) technology for the Cortex-A9 processor on the TSMC 40LP process, including ultra low threshold voltage (uLVT). The combined solution is available for license from ARM to accelerate the implementation of ARM processors.

POP IP features core-hardening acceleration technology that uses the latest ARM Artisan advanced physical IP to achieve industry-leading power, performance and area (PPA) metrics. In the combined solution, the POP IP is tightly coupled to Cadence Encounter RTL-to-GDSII technologies, including RTL Compiler-Physical and the breakthrough clock concurrent optimization (CCOpt) design technology, resulting in market-leading, certified benchmarks for Cortex-A9 implementations using POP IP.

POP solutions consist of three critical elements necessary to achieve an optimized ARM processor implementation. First, it contains Artisan physical IP standard cell logic and memory cache instances that are specifically tuned for a given ARM processor and foundry technology. Second, it includes a comprehensive benchmarking report to document the exact conditions and results ARM achieved for the processor implementation across an envelope of configuration and design targets. Finally, it includes the detailed implementation knowledge including floor plans, scripts, design utilities and a POP Implementation Guide, which enables the end customer to achieve similar results quickly and with lower risk.

The Cadence-ARM POP IP is the first in a series of combined solutions enabling designers to improve performance, power and time-to-market for ARM Cortex-A series processor-based system-on-chips (SoCs).

More info: Cadence Design Systems, Inc. | ARM