EDA Blog - electronic design automation, embedded systems, ic

Share/BookmarkSubscribe

2013 Design and Verification Conference Issues Call for Papers

Posted by Ken Cheung in Events, Training on Thursday, July 26, 2012

Accellera Systems Initiative has issued a call for papers for the 2013 Design and Verification Conference. The deadline to submit an extended abstract (800 to 1,000 words) is August 21st. DVCon is a conference for the application of languages, tools and methodologies for the design and verification of electron systems and integrated circuits. DVCon 2013 will take place February 25-28, 2012 at the DoubleTree Hotel in San Jose, California.

DVCon submissions should include:

  • A title (authors are encouraged to be creative)
  • Name, affiliation, phone number and email addresses for all authors
  • An introduction that specifies the context and motivation of the submission
  • A summary of the specific contributions of the authors work
  • A summary that highlights results
  • To evaluate the author’s contribution, some results must be specified
  • References, if appropriate
  • The extended abstract can be at most two pages (800 to 1,000 words)
  • Abstract can be formatted in a single or double column

2013 DVCon Topics of Interest

  • Formal and semi-formal techniques
  • Static verification techniques
  • ESL and/or TLM for system-level design and verification
  • Hardware/software co-design and co-verification
  • Mixed-signal design and verification
  • Power-aware design and verification
  • System-on-Chip design and verification
  • Network-on-Chip design and verification
  • Using multiple HDLs and/or HVLs in a design cycle
  • Automated stimulus generation methods
  • Verification techniques that really work (and what did not work)
  • Verification process and resource management
  • Assertion-based verification
  • Coverage-driven verification
  • Design and verification IP experiences, good and bad
  • Debug techniques for HVL testbenches and complex software-style testbenches
  • Debug techniques for SoCs with black-box and grey-box IP
  • Debug techniques for ESL and abstract models
  • Software engineering techniques for advanced testbenches
  • Deployment of recently approved standards

More info: DVCon Abstract Submission

Related Posts with Thumbnails

Custom Search

EDA Blog Newsletter
Don't have time to visit EDA Blog everyday? Then sign up for our free newsletter. We'll send you an email when we have something to share with you. Your email address will be kept confidential and we will not share, sell, or rent it to anyone. You can unsubscribe at any time by clicking a link in the email.

Enter your email address to sign up for our free newsletter:  

If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.