Synopsys introduced version 2012.06 of their IC Compiler software. The latest release of IC Compiler release includes multiple advances to support giga-performance design. IC Compiler 2012.06 helps IC designers achieve higher clock frequencies more efficiently. Synopsys’ IC Compiler 2012.06 features optimizations that can boost operating clock speeds, expanded support for highly fragmented floorplans and new technologies that address advanced process effects.
The IC Compiler 2012.06 release contains several new technologies for improving design frequency. Clock distribution using a mesh structure has been a staple of high performance designs to minimize variation. However, mesh flows are complex and require expert user knowledge to manage power efficiently. Multi-source clock tree synthesis (CTS) is a new technology that leverages automated clock tree and mesh techniques to provide better variation tolerance than traditional CTS, while consuming less power than a mesh.
The latest release of IC Compiler features new algorithms that leverage advanced process effects to improve timing, reduce buffer count and create more robust circuits for reduced variability. With shorter time-to-market windows and the need for a more integrated feature set, designs are seeing increasing intellectual property (IP) reuse. IP-dominated designs often have highly fragmented floorplans characterized by narrow channels between blocks and a large number of macros and pipelined registers. IC Compiler 2012.06 can improve timing and routability for such designs.
The 2012.06 release of IC Compiler also includes enhancements that enable designers to achieve target frequency. Transparent interface optimization technology has been improved to provide better timing and faster time to results. In-Design physical verification enables power network verification and improved runtime for foundry-required metal fill insertion.
More info: Synopsys, Inc.