Cadence Design Systems has added new capabilities in their PCI Express Verification IP. The Cadence PCIe VIP now offers more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels. The Cadence PCIe VIP is a broad, highly differentiated, and proven solution with distinct advantages for PCI Express verification. Cadence’s VIP solution includes over 40 interface protocols and more than 6,000 memory models that have been deployed in thousands of designs.
The latest release of the Cadence PCI Express Verification IP addresses the full spectrum of PCIe applications and supports the latest specifications — including SR-IOV, MR-IOV, NVMe and PIPE4. This helps engineers to quickly implement designs with the newest PCI Express interfaces.
The Cadence PCIe VIP enables efficient and thorough verification of SoCs. A new performance measurement utility helps engineers optimize designs for improved link utilization, throughput, latency, and power. The PCIe TripleCheck IP Validator verifies that IP blocks comply fully with protocol specifications. TripleCheck combines the three most critical components of verification in a single, easy-to-use environment: a test suite, coverage model, and verification plan covering all sections of the PCIe specification including PL, DLL, TL, Power Management and Error Handling. All the components are automatically customized to the user’s individual configuration.
The Accelerated VIP gives a 100x boost in simulation throughput of Universal Verification Methodology (UVM)-compliant testbenches using the Cadence Palladium XP verification computing platform. This simulation-acceleration usage mode enables designers perform full-chip simulation that would otherwise be impossible or impractical in RTL simulation alone.
Cadence PCI Express Verification IP Features
- Support for the new PCIe PIPE4 specification
- New performance measurement features critical for optimizing PCIe implementation
- TripleCheck test suite, coverage and verification plan to shorten and ease testing for full PCIe specification compliance
- Accelerated PCIe VIP that drives the verification speed required for large SoCs
More info: Cadence PCI Express Verification IP (VIP)