Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.
The SMIC 40LL process technology features advanced immersion lithography, strain engineering, ultra shallow junction and ultra low-k dielectric. The 40nm process provides the optimized power and performance required of mobile multimedia and consumer devices. Synopsys’ IP on SMIC’s advanced low-power process enables designers to incorporate more functionality into their advanced system-on-chip (SoC) designs with less risk and faster time to market.
Synopsys DesignWare IP available now or scheduled to be available later this year on the SMIC 40LL process includes:
- Interface IP for widely used protocols such as USB 2.0/3.0, PCI Express 2.0/1.1, MIPI, SATA, DDR, and HDMI that reduces interoperability risk
- Audio codec and data converter IP, optimized for a wide range of high-performance, low-power applications
- Embedded memories and logic libraries that enable designers to achieve both high speed and low power across the entire SoC
Synopsys DesignWare IP for SMIC 40LL Process Highlights
- 15 Synopsys DesignWare IP products available on SMIC’s 40LL process technology enable designers to incorporate functionality more easily into advanced low-power SoCs
- Proven interface PHY IP, including PCI Express, USB and DDR, helps SoC designers ensure interoperability with the latest standards
- High-quality analog IP, including audio codecs and data converters, helps designers meet low-power, application-specific SoC requirements
- Embedded memories and logic libraries for the SMIC 40LL process enable design teams to optimize entire SoC designs for both speed and energy efficiency