SMIC-Synopsys Reference Flow 5.0 Extends 40nm Low Power Capabilities
Synopsys and Semiconductor Manufacturing International Corporation (SMIC) released version 5.0 of their 40-nanometer RTL-to-GDSII reference design flow. The SMIC-Synopsys Reference Flow 5.0 enables IC designers to accelerate their designs into manufacturing through the combination of SMIC’s 40nm process technology and Synopsys’ technology-leading design solutions. The SMIC-Synopsys Reference Flow 5.0 is available now.
The latest RTL-to-GDSII reference design flow includes a broad range of automated low power and high-performance capabilities through Synopsys’ entire tool suite. The production-proven flow gives engineers immediate access to both high-performance and low power design solutions tailored for SMIC’s 40-nanometer low power process. This provides SMIC customers the differentiated performance and power results needed in today’s chip designs.
The SMIC-Synopsys reference flow features new high-performance design techniques, including automated clock mesh synthesis, to increase performance and responsiveness of a system on chip (SoC), plus a gate array engineering change order (ECO) flow that allows a designer to quickly achieve design closure without having to start from scratch with a redesign. The reference flow also includes support for low power techniques such as power-aware clock tree synthesis, power gating and physical optimization, driven by the IEEE 1801 low power design intent standard.
SMIC-Synopsys Reference Flow 5.0 Highlights
- Common Power Format (CPF)
- Realization of low power targets with various low power technologies, including power shut-off, multi-supply, multi-threshold library utilization, clock gating
- Multi-Mode Multi-Corner (MMMC) analysis and optimization in the EDI system
- Full-chip flat implementation with in-design signoff analysis in a single environment in EDI System
- Concurrent optimization and convergence, and power-domain aware synthesis with RC Physical
- Low power validation with Conformal Low Power
- Logic equivalence check with Conformal Equivalence Check
- Static and dynamic power and IR drop sign-off with EPS
- Advanced MMMC timing and SI sign-off with ETS
- Efficient physical verification by PVS which is also integrated with the EDI system
- Thickness variation prediction by CCP, and thickness-ware parasitic RC extraction with QRC
- Integration with SMIC 40nm technology, including libraries, IP, technology files and design rules
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