Cadence Design Systems and Samsung Electronics teamed together on a 20-nanometer design methodology. Their 20nm digital design methodology features double patterning technology for joint customer deployment and internal test chips. The new design methodology enables design at 20 nanometers and future process nodes. It is ideal for mobile consumer electronics.
Double patterning is a key new approach to lithography that enables higher routing density for advanced process nodes. Double patterning splits each metal layer of designs into two masks for chip fabrication, enabling higher metal density and smaller silicon area for process technologies at 20-nanometers and below.
For the digital parts of the chip, the Encounter Digital Implementation (EDI) System provided an automated methodology for double patterning-correct placement and routing using its patent-pending FlexColor technology for real-time colorization. The EDI System delivers die-area efficiency and DRC accuracy during placement, optimization and routing. For final signoff, engineers used the Cadence Encounter Timing System, Encounter Power System and QRC Extraction, which has been enhanced to accept multiple extraction values to manage variation in double-patterning alignment.
More info: Cadence Design Systems, Inc.