Synopsys introduced an integrated hybrid prototyping solution. The out-of-box solution features Synopsys’ Virtualizer virtual prototyping and Synopsys’ HAPS FPGA-based prototyping. By integrating the strengths of Virtualizer virtual prototyping with HAPS FPGA-based prototyping using the UMRBus physical link, Synopsys enables designers to develop fully operational SoC prototypes much faster and earlier in the design cycle, and accelerate software development and full system validation. The Synopsys hybrid prototyping solution is available now to early adopters.
The Synopsys hybrid prototyping solution consists of the following products:
- HAPS-60 Series System
- HAPS UMRBus Interface Kit
- Optional: Virtualizer (for SystemC support)
- HAPS-60 Co-Sim and Transactor-Based Validation (TBV) Suite
- Certify multi-FPGA partitioning and implementation software
- Optional: VCS-MX (for co-simulation support)
Synopsys’ hybrid prototyping solution blends the strengths of both Virtualizer virtual and HAPS FPGA-based prototyping to enable software development and system integration much sooner in the project lifecycle. By using Virtualizer virtual prototyping for new design functions and HAPS FPGA-based prototyping for reused logic, designers can start software development up to 12 months earlier in the design cycle. In addition, Synopsys’ hybrid prototyping solution enables designers to accelerate hardware/software integration and system validation.
Synopsys’ hybrid prototyping solution enhances software stack validation through very high-speed execution of processors using a Virtualizer virtual prototype. It allows direct connection to real-world I/O model interfaces through analog PHYs or test equipment attached to a HAPS FPGA-based prototype. In addition, designers can take advantage of existing RTL or IP in the FPGA-based prototype and new functions in SystemC transaction-level models, which are faster to implement and available much sooner in a project lifecycle.
Synopsys Hybrid Prototyping Solution Highlights
- Integrates Virtual and FPGA-Based Prototypes
- Start multi-core SoC prototyping earlier
- Achieve high-performance execution of system-level models with real-world interface connectivity of hardware
- Partition SoC design to maximize overall performance
- Accelerate system prototype bring-up
- Improve software debug visibility
- Easily integrate ARM Cortex Processor models, AMBA protocol transactors and DesignWare IP into a single hybrid prototype
More info: Synopsys Hybrid Prototyping Solution (pdf)