Cortus Introduces APS5 Embedded Microcontroller IP Core

Cortus APS5 microcontroller IP core

Cortus announced their APS5 embedded microcontroller. The Cortus APS5 is a 32-bit general purpose CPU. The processor IP is designed for demanding embedded systems. It features a high performance integer unit and an instruction cache. The APS5 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3R.

Cortus APS5 embedded microcontroller

The Cortus APS5 microcontroller IP core combines good integer computational performance with a high maximum clock frequency. The processor IP has a five to seven stage integer pipeline and out-of-order completion. This ensures that most integer instructions (load and stores included) are executed in a single cycle. The APS5 is ideal for ASICs requiring more complex processor subsystems, such as those with instruction and data caches or co-processors..

The APS5 has been designed to provide scalable computing performance. It includes an instruction cache and an optional data cache. Performance can be increased with symmetric multi-processing (SMP) configurations, such as dual- or quad-core. For example, a single APS5 core offers 1.93 CoreMarks/MHz, while a dual-core configuration benchmarks at 3.51 CoreMarks/MHz. For SMP configurations, a coherent data cache with snoopy protocol is available. Other applications may benefit from heterogeneous APS5/APS3R configurations.

The Cortus APS5 CPU core has a silicon footprint of 0.088 mm2 in 90 nm (UMC). APS5 interfaces to all of Cortus’ peripherals, including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. In addition, the APS toolchain and IDE (for C and C++) is available to licensees free of charge. Ports of RTOS’s are also available.

Cortus APS5 Microcontroller IP Core Features

  • High throughput RISC core
  • Excellent code density
  • Sixteen 32 bit general purpose registers
  • High computational performance
  • Expandable through co-processor interface
  • Instruction cache
  • Optional data cache
  • Most instructions are single cycle, including load and store
  • Optional memory management
  • Optional memory protection unit
  • Integer divider
  • Dual and multi-core capable
  • 5-7 Stage Pipeline
  • Integer Multiply
  • All necessary tools are available free of charge
    • Eclipse based IDE
    • GNU GCC and all utilities ported
    • GNU GDB Debugger available
    • Debug via JTAG

More info: Cortus APS5 Embedded Microcontroller (pdf)