TSMC Certifies Synopsys Design Implementation Tools for 20nm Process
TSMC has given Phase I Certification to Synopsys design implementation tools for TSMC’s 20nm process. Synopsys’ Galaxy Implementation Platform features comprehensive support for TSMC’s latest set of 20-nm design rules. The certified tools from TSMC’s Open Innovation Platform and its ecosystem members help engineers create products that meet aggressive power, performance and area targets.
Certified products include Synopsys’ IC Compiler for physical design; IC Validator for DRC and LVS; StarRC for extraction; and Galaxy Custom Designer for custom implementation. Certification of PrimeTime for static timing analysis is in progress. Certification covers all the relevant 20nm technology files including routing rules, verification runsets, extraction rundecks and Interoperable Process Design Kit (iPDK).
TSMC Certified Synopsys Implementation Tools
- IC Compiler
Innovative-patterning compliant placement, and correct-by-construction innovative-patterning-clean routing help provide the optimal area and performance that can be reliably decomposed during manufacturing - IC Validator
New, native graph-based coloring ensures layout decomposition and in-design integration with IC Compiler for accurate, scalable signoff of 20-nm designs - PrimeTime
Support for multi-valued SPEF model variation impact on timing due to innovative patterning - StarRC:
Parasitic variation modeling solution addresses the effects of innovative patterning technology due to mask misalignment and other critical technology requirements - Custom Designer
Productivity aids, such as connectivity assisted editing, with support for new local interconnect and cut poly, 20-nm constraints, and correct-by-construction variable size via creation help manage design-rule complexity
More info: Synopsys 20nm Solution
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