Cadence Adds In-Circuit Acceleration to System Development Suite, Expands VIP Catalog
Cadence Design Systems made two announcements today. First, the company developed new in-circuit acceleration based on the Incisive and Palladium XP platforms for their System Development Suite. Cadence’s second announcement involved extensions to the Verification IP Catalog for acceleration and emulation that enable engineers to go beyond simulation to speed verification of large-scale SoCs, sub-systems and systems.
According to Cadence, the inefficiencies and performance limitations introduced by traditionally disconnected development platforms combined with verification IP applicability being limited to simulation-only approaches are posing a threat to engineers designing systems and SoCs for consumer and wireless electronics being able to deliver products on time. Cadence’s new in-circuit acceleration in the System Development Suite and the extension of their Verification IP Catalog enable open, connected and scalable system-level development.
System Development Suite (SDS) with In-Circuit Acceleration
The System Development Suite now offers a single heterogeneous environment for system-level verification based on the Incisive and Palladium XP platforms, which enables designers to leverage both the high speed and real-world interfaces of traditional in-circuit emulation environments combined with the advanced analysis capabilities available in RTL simulation. Design teams are no longer forced to create and maintain both environments, spend unnecessary time and effort to reproduce bugs, or remodel all system components targeted for one environment. The new in-circuit acceleration enables teams for simulation acceleration and emulation to deploy a common unified verification environment. This speeds efficiency during system-level validation and root cause analysis by a factor of up to ten. In-Circuit Acceleration enables a new paradigm of system-level debug productivity while maintaining full In-Circuit Emulation performance.
Expanded Verification IP (VIP) Catalog for Acceleration and Emulation
The Cadence VIP catalog now includes Accelerated VIP for the following interface standards: ARM’s AMBA AXI 3/4 and ACE, PCI Express 2.0/3.0, USB 3.0, 10Gb Ethernet, SATA 3, and HDMI 1.4. Universal Verification Model (UVM)-compatible Accelerated VIP enables designers to smoothly transition from simulation to acceleration, in-circuit acceleration, and in-circuit emulation. This helps engineers to verify complex Systems and SoCs that are simply too large for effective verification using traditional RTL simulation.
More info: Cadence Design Systems, Inc.
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