Sigrity Launches XcitePI IO Interconnect Model Extraction

Sigrity XcitePI chip-level analysis tools for pre- and post-layout design improvement

Sigrity launched their XcitePI IO Interconnect Model Extraction and Assessment software. The tool provides accurate system-level analysis of high-speed channels and buses by generating precise chip IO power/ground and signal interconnect models. XcitePI IO Interconnect Model Extraction is available on Windows and Linux platforms. Prices start at $108,000 for a 3-year license. The new tool is part of Sigrity’s XcitePI chip-level analysis family that supports both pre- and post-layout design improvement.

The Sigrity XcitePI IO Interconnect Model Extraction tool offers built-in I/O quality assessment capabilities that help engineers to quickly check IO power/ground robustness and signal electrical performance to identify potential design defects. XcitePI IO Interconnect Model Extraction also enables quick assessment of power and ground quality along with signal performance at every IO cell. Graphical representations of electrical performance at each cell help designers quickly identify weak or problematic physical areas and perform what-if analysis to rapidly improve the design.

XcitePI produces high resolution chip IO models that are compact in size. The models can be used in conjunction with SPICE-compatible circuits for system-level simulations. Taking chip layout data in GDSII or LEF/DEF formats, the XcitePI tool can generate a SPICE netlist consisting of a fully distributed IO power/ground model and IO signal connections from IO cells to bumps.

XcitePI IO Interconnect Model Extraction accounts for all coupling between the power, ground and signals on the chip, the distributed capacitance associated with the power and ground systems, and on-chip decoupling capacitors connected to the power and ground systems. The model produced includes external terminals on the bump side with Sigrity’s Model Connection Protocol (MCP) header information for easy connection to IC package models. The model also includes external terminals at the IO cell level to streamline connection with targeted driver/receiver models.

According to Sigrity, accurate models of chip IO interconnects that fully represent the distributed nature of power, ground and signals as well as their electromagnetic coupling effects were not available in commercial EDA flows prior to XcitePI IO Interconnect Model Extraction. The new tool fills this gap and builds on Sigrity’s capability to provide the accuracy and efficiency needed to model and simulate chip-to-chip signal and power integrity for today’s challenging high-speed designs.

More info: Sigrity XcitePI