CDNLive! EMEA 2012 to Take Place in Munich, Germany from 14-16 May

CDNLive! EMEA user conference ~ Cadence Design Systems

Cadence Design Systems will hold the CDNLive! EMEA user conference from May 14-16 at the Dolce Hotel in Munich/Unterschleissheim. The annual user conference will share fresh new and best practices that address all aspects of design and IP creation, integration, and verification. Attendees of CDNLive! EMEA will get to explore new techniques for realizing advanced silicon, SoC, and systems.

CDNLive! EMEA Topics

  • Opportunities, Challenges, and Collaboration
  • New Solutions in Mixed-Signal Design
  • Semiconductors, core of a sustainable amazing world
  • Thermal and mCAD-Integration
  • Advanced Mixed-Signal Verification and Implementation Enablement
  • Improving Verification Performance for Advanced Node SoCs
  • Achieving best power, performance and area for ARM processor-based Designs
  • Allegro Productivity
  • DDR IP
  • Cadence System Development Suite
  • New concept in debug – Fast Track your bugs using the new Incisive Debug Analyzer
  • IO Planning for large pin count FPGA’s
  • Detection of FOX Parasitic MOS Structures in Layout, Using Cadence SKILL
  • Coverage driven requirements management
  • Lead institution Analog Mixed-Signal Design Methodology
  • Investigating the static and dynamic error mechanisms of D/A converters
  • Verification of an analog frontend using enhanced Specman driven Real Value Modeling stimuli
  • Deep Dive on Ethernet IP
  • Lead institution Dependability and Design for Testability
  • Top level verification of a mixed analog digital SOC using AMS-Designer
  • Specman based technical solution for a TLM2 verification component used in a real-world project
  • Robust Predictability of Parasitic Effects for RF Designs using RLCk Extraction
  • Functional Verification and Verification IP
  • Silicon Validation of Cadence’s Digital Design Flow for GlobalFoundries 28SLP process
  • Apps for OrCAD and Allegro
  • PCI Express IP Overview
  • Hierarchical spare cell Placement
  • Modeling and Simulation of a Modulated Electro-Mechanical Continuous-Time Lowpass Sigma-Delta Modulator
  • Automation of switch insertion and power network generation in 28nm power-shutoff designs: Issues and solutions
  • Combining Spectre and PSpice – an opening for new design methods
  • Memory Controller IP Overview
  • Integration of full-custom cells in a standard-cell based flow
  • Using ADE XL for Sign-Off Simulations/Regression
  • Do it Once, do it Timely
  • CRM integrated part management for OrCAD and Allegro
  • Wide I/O and TSV: State of the Art
  • Variability Aware Design & Analysis
  • Using “Apps” to Take Formal Analysis Mainstream
  • High-performance processor-based design
  • Single-Canvas Package-Board Co-design
  • DDR Design-In-Kit
  • Xilinx Zynq-7000 EPP Virtual Platform for Software Development
  • Register Modeling in UVM
  • Advanced analog mixed-signal verification with UVM-MS
  • One for all! Unified UVM Interface for any VIP and memory model
  • Functional and MMMC signoff-driven ECO
  • Power Delivery Network design
  • IP selection and Fast and accurate estimation of IC size, power, performance, and cost
  • Coding refinements between functional/virtual-prototype model and synthesizable SystemC models
  • Using Property Checking to find a difficult bug in DMA block: Industrial Experience
  • Flow and library validation on a 22nm SOI testchip – The Greenseed project
  • PCB and Package Co-design and Co-optimization using Simplified Workflow from Cadence SiP to CST STUDIO SUITE 2012
  • DFT Architecture and ATPG for JEDEC Wide-IO Memory-on-Logic 2.5D/3D-Stacks
  • Early Power Estimation in a Mixed-Signal Environment using UVM and RTL Compiler
  • Formal Verification of Static Properties in Clock Gating Modules
  • Multi voltage domain, multi VT low power physical implementation by using Cadence tool suite
  • More Advances in Creepage and Air Gap Analysis in Electromechanical Products with NEXTRA
  • Security-Aware Design and Verification Techniques with RTL Compiler
  • Family of Mulitchannel ASICs for Measurements Electrical Activity of Neural Networks
  • Fast & complete formal verification of a complex data preprocessor using out-of-the-box Cadence scoreboard properties
  • Power Calculation From early estimation to silicon correlation
  • Analog and Mixed Signal Die to Package checks
  • SyMX – Model Crossover between Simics and SystemC/TLM Virtual System Platforms
  • Early, functional unit based, power estimation for wireless baseband processors
  • Circuit optimization procedure combines OrCad and Matlab
  • Altis Multi Process PDK Development Platform for fast Creation and QA of Design-Ready IC 6.1.5 PDKs
  • A UVM-based verification methodology for RFID enabled smart sensor systems
  • Implementation of a flexible, low power and high performance 4G baseband processor with the Cadence CPF flow
  • Constraint managed, Team-based design methology with Design Re-use
  • Area-Based Design Rule Aware Error Correction
  • Advanced Verification Techniques for the Mixed-Signal Domain
  • Design Driven By DFM
  • Leveraging Virtual Platforms in Compute Sub-System Design
  • A receiver – TDC chip set for accurate pulsed time-of-flight lase ranging
  • Analog BIST generation within the Cadence Design Flow
  • Metric-Driven Verification Flow for AMS IPs
  • Multi Level Partitioning Flow for Giga Scale Designs
  • Board-to-board co-design – multiple board mechanical solution
  • Sequences: Formalizing software programming sequences to enhance HW/SW integration
  • Model-based Design Space Exploration and Synthesis Flow for Digital Signal Processing Algorithms
  • Verilog-AMS Verification of ADC Soft IP cores
  • Method of On-the-fly chip verification
  • Hierarchical cpf usage in ST-HED low power flow
  • Interconnect Floor Planning – plan, check, commit approach for board connectivity
  • Virtual Platforms: technology, application and experiences
  • Looking for uninitialized Flip-Flops with Conformal Constraint Designer (CCD)
  • SystemC based Model Refinement Flow for System Verification of a GNSS Receiver Frontend
  • Customer Acceptance Test Program accelerates adoption of new IC releases for ST’s PDKs
  • Auto-generated UVM framework for fast and reusable verification
  • Accurate Clock Tree Prototyping for Gigascale Designs
  • Chip-PCB Co-Simulation with Extracted PCB Net Models
  • HW/SW co-verification of a microcontroller debug system
  • Automated Modular ECO Flow – A Solution for doing Chip Revisions as ECO

More info: CDNLive! EMEA 2012