SynaptiCAD Verilog2VHDL Tool Now Supports Verilog 2005
SynaptiCAD rolled out a new version of their Verilog2VHDL tool. The SynaptiCAD V2V tools translate bidirectionally between Verilog and VHDL source code. The translators are are ideal for converting behavioral and/or RTL-level code to a preferred design language. The V2V translation software is available on Windows and Linux. The SynaptiCAD software can be licensed on either a permanent or leased basis, and both floating and node-locked versions are available.
The SynaptiCAD VHDL2Verilog tool features several enhancements. These include better generation of bit ranges for parameters generated from VHDL constants and an option to translate VHDL integer literals into fixed-length bit strings for synthesized designs.
The SynaptiCAD Verilog2VHDL tool now supports the following Verilog 2005 constructs:
- Multi-dimensional arrays
- Signed regs and nets that convert to VHDL numeric_std.signed data types
- Verilog 2005 event control expressions such as @(posedge foo, posedge bar)
- New localparam keyword
- Module parameter port lists
- Named parameter assignments
The V2V tools are stand-alone command-line programs, but SynaptiCAD’s graphical HDL debugger, BugHunter Pro, can also be used to configure options to the translators and launch them on files in an HDL design project. Using BugHunter in combination with the V2V tools, users can quickly translate a design, then compile and simulate both the original files and the translated files to compare their output, make any necessary corrections, then resimulate. The BugHunter debugger is compatible with the following VHDL and Verilog simulators: SynaptiCAD’s Verilogger Extreme, Cadence’s Incisive, Synopsys VCS, Mentor Graphic’s ModelSim, and Aldec’s ActiveHDL.
More info: SynaptiCAD
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.