Cadence Design Systems introduced their TripleCheck IP Validator. The test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading test bench languages. Cadence TripleCheck IP Validator is available now for PCIe Gen 3. Cadence has support for several additional protocols in development for release later this year.
TripleCheck IP Validator is the latest addition to the Cadence Verification IP (VIP) Catalog. The Cadence VIP Catalog simplifies and accelerates compliance testing of interface design IP. It helps engineers quickly and thoroughly verify their implementations of standard interfaces, such as PCI Express 3.0. TripleCheck is integrated with the Cadence VIP PureView user interface, and it provides three main capabilities:
- Test Suite
TripleCheck provides a library of test sequences, including directed tests for basic protocol compliance and constrained-random sequences that provide exhaustive testing.
- Coverage Model
Pre-defined coverage models for both e and SystemVerilog capture all data items and state machine transitions in order to track and measure verification progress.
- Verification Plan (vPlan)
TripleCheck provides a verification plan derived from the protocol specification. The plan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped to the plan.
TripleCheck IP Validator builds on the earlier generations of Cadence compliance solutions: PureSuite and Compliance Management System (CMS). TripleCheck combines features of both solutions and includes significant new capabilities. TripleCheck IP Validator helps engineers deal with the growing complexity of standard interfaces, typified by high speed interconnects such as the PCI Express 3.0 standard and cache coherent SoC fabrics such as AMBA 4 AXI Coherency Extensions (ACE).
More info: Cadence Design Systems, Inc.