Xilinx introduced their Vivado Design Suite, which is an IP and system-centric design environment for accelerating the design of all programmable devices. The Vivado Design Suite version 2012.1 is available as part of an early access program. Public access will start with version 2012.2 early this summer, followed by WebPACK availability and Zynq-7000 extensible processing platform (EPP) support later in the year. ISE Design Suite Edition customers with current support will be provided the new Vivado Design Suite Editions in addition to ISE at no additional cost.
The Xilinx Vivado Design Suite not only speeds the design of programmable logic and I/O, but accelerates programmable systems integration and implementation into devices incorporating 3D stacked silicon interconnect technology, ARM processing systems, Analog Mixed Signal (AMS), and a significant percentage of semiconductor intellectual property (IP) cores. Vivado tools can improve productivity over competing development environments by a factor of four.
The Vivado Design Suite provides a highly integrated design environment (IDE) with a completely new generation of system-to-IC level tools, all built on the backbone of a shared scalable data model and a common debug environment. It is also an open environment based on industry standards such as the AMBA4 AXI4 interconnect specification, IP-XACT IP packaging metadata, the Tool Command Language (Tcl), Synopsys Design Constraints (SDC) and others that facilitate design flows tailored to the user’s needs. Xilinx architected Vivado tools to enable the combination of all types of programmable technologies and scale up to 100-million-ASIC equivalent gate designs.
The Vivado IDE includes electronic system level (ESL) design tools for rapidly synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems with 3X faster simulation, while hardware co-simulation provides 100X more performance.
Vivado Design Suite includes a hierarchical device editor and floor planner, a 3-15X faster logic synthesis tool with support for SystemVerilog, and a 4X faster, more deterministic place and route engine that uses analytics to minimize a cost function of multiple variables such as timing, wire length and routing congestion.
Incremental flows allow for engineering change order (ECO) induced changes to be quickly processed by only re-implementing a small part of the design, while preserving performance. In addition, leveraging the new shared scalable data model, the tools provide power, timing and area estimates at every stage of the design flow, enabling up front analysis and then optimization with integrated capabilities such as automated clock gating.
More info: Xilinx, Inc.