EDA Blog - electronic design automation, embedded systems, ic

Mentor Graphics Introduces Questa Functional Verification Platform v10.1

Mentor Graphics rolled out version 10.1 of their Questa functional verification platform. The 10.1 release features increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low power verification with comprehensive Unified Power Format (UPF) support. Questa functional verification platform is a tightly integrated solution for the functional verification of complex System-on-Chip (SoC), ASIC and FPGA designs.

Questa Platform v10.1 Highlights

• Questa Multi-Core simulation technology for large designs that can take advantage of modern compute systems by partitioning the design to run on multiple CPUs or computers in parallel, while maintaining a single database for debug and coverage closure
• Questa Multi-Core is ideal for large designs with long simulation times where designers have experienced from 2-5x run time improvement depending on the number of cores used
• Compiler and simulation engine now makes it easier to create a common testbench for use across Questa simulation and Veloce emulation platforms creating a fast path to performance acceleration
• First verification platform with a UVM-aware debug solution that gives engineers essential information about the operation of their dynamic, class-based testbenches in the familiar context of source code and waveform viewing that RTL designers have used for years
• Additional UVM-specific views show the component hierarchy, class definition tree, and other UVM settings specific to a testbench to make it easier to understand the operation of the verification environment
• Includes a new Run Manager control panel that makes it easier to control, configure, analyze and automate regression environments
• With Questa Run Manager, engineers have been able to reduce their regression run times from days to hours
• Can automatically import their existing SystemVerilog constraints and covergroups, accelerating coverage closure with minimal time and effort
• Automatically generates SystemVerilog covergroups, simplifying the creation and understanding of coverage models
• Support for UPF 2.0, as well as multiple new static and dynamic power checks used for both register transfer level (RTL) and gate level power verification

More info: Mentor Graphics Corporation

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