Semiconductor Manufacturing International Corporation (SMIC) announced a low-power, advanced-node IC design reference flow. The new reference flow features Cadence Encounter digital technology and SMIC’s 40-nanometer manufacturing process. The interoperable, low-power, Common Power Format-based flow helps engineers accelerate and differentiate their low-power, high-performance chips.
The SMIC-Cadence flow gives design teams a predictable and accelerated path to complex SoC designs for a wide range of low-power applications, including the latest consumer electronics products such as tablets and smartphones. The reference flow helps designers achieve faster time-to-volume for advanced low-power 40-nanometer designs.
The new 40nm reference flow flow automates designs with advanced power management features. The production-proven methodology is fully incorporated across the complete and integrated Cadence RTL to GDSII flow, which includes Encounter RTL Compiler, Encounter Conformal Low Power, Encounter Digital Implementation System, Encounter Timing System, Encounter Power System, Cadence QRC, Cadence CMP Predictor and Cadence Physical Verification System.
With the new SMIC-Cadence flow, engineers will benefit from a comprehensive set of digital technologies. These include flat power aware implementation with timing and signal integrity closure, power domain aware physical synthesis, closed loop low-power verification and physical verification.