International Symposium on Quality Electronic Design Features 100 Papers

The International Symposium on Quality Electronic Design will take Monday, March 19 through Wednesday, March 21, 2012 at TechMart, Santa Clara. The 13th annual ISQED features talks by experts that cover multiple topics related to electronic design and semiconductors. Speakers and attendees include designers, users, and providers of integrated circuits (IC) and systems, semiconductor packaging, assembly and test technology, as well as Electronic Design Automation (EDA) tools. The conference includes 22 technical sessions with close to one hundred papers. It also features keynotes, tutorials, workshops and exhibits with a focus on the latest innovations in electronic design.

2012 ISQED Topics

  • Physical-Design-Friendly Hierarchical Logic Built-In Self-Test – A Case Study
  • A Self-Testable SiGe LNA and Built-in-Self-Test Methodology for Multiple Performance Specifications of RF Amplifiers
  • Improved Path Clustering for Adaptive Path-Delay Testing
  • TSV and DFT Cost Aware Circuit Partitioning for 3D-SOCs
  • A Design-For-Test Apparatus for Measuring On-Chip Temperature with Fine Granularity
  • Reliable System Design
  • Wearout-Aware Compiler-Directed Register Assignment for Embedded Systems
  • Process-Variation Aware Mapping of Real-Time Streaming Applications to MPSoCs for Improved Yield
  • Single Fault Reliability Analysis in FPGA Implemented Circuits
  • Low Complexity Cross Parity Codes for Multiple and Random Bit Error Correction
  • Delay Insensitive Code-Based Timing and Soft Error-Resilient and Adaptive-Performance Logic
  • System Frameworks and Tools
  • Online Mapping of Embedded Applications on MPSoCs
  • A Particle Swarm Optimization Approach for Synthesizing Application-specific Hybrid Photonic Networks-on-Chip
  • A Preliminary Study on System-level Impact of Persistent Main Memory
  • Optimal Microarchitectural Design Configuration Selection for Processor Hard- Error Reliability
  • Noc-based platform for embedded software design: An extension of the Hellfire Framework
  • Thermal and Power in 3D ICs
  • Thermal Via Structural Design in Three-Dimensional Integrated Circuits
  • Functional Test Pattern Generation for Maximizing Temperature in 3D IC Chip Stack
  • Thermal analysis of 3D integrated circuits based on discontinous Galerkin finite element method
  • Full-chip Thermal Analysis of 3D ICs with Liquid Cooling by GPU-Accelerated GMRES Method
  • Leakage-Aware Performance-Driven TSV-Planning Based on Network flow Algorithm in 3D ICs
  • A 3D IC Designs Partitioning Algorithm with Power Consideration
  • Low Power Communication Circuits
  • Embracing Local Variability to Enable a Robust High-Gain Positive-Feedback Amplifier: Design Methodology and Implementation
  • An Ultra-Low Voltage Digitally Controlled Low-Dropout Regulator with Digital Background Calibration
  • Dynamically biased low power High performance 3.3V output buffer in a single well bulk CMOS 1.8V oxide 45nm process
  • Design of an Efficient NoC Architecture using Millimeter-Wave Wireless Links
  • A Novel Robust Signaling Scheme for High-Speed Low-Power Communication over Long Wires
  • An Extended-Range Incremental CT Sigma Delta ADC with Optimized Digital Filter
  • Process-Induced Variability and Hot Spot Detection
  • Test Structure, Circuits and Extraction Methods to Determine the Radius of Influence of STI and Polysilicon Pattern Density
  • Post-Placement Lithographic Hotspot Detection and Removal in One-Dimensional Gridded Designs
  • On Lithography Aware Metal-Fill Insertion
  • Understanding, Modeling, and Detecting Pooling Hotspots in Copper CMP
  • Methodology for Analysis of TSV Stress Induced Transistor Variation and Circuit Performance
  • High Performance Electrical Driven Hotspot Detection Solution for Full Chip Design using a Novel Device Parameter Matching Technique
  • Emerging Topics in EDA
  • Fast Delay Estimation with Buffer Insertion for Through-Silicon-Via-Based 3D Interconnects
  • Functional Composition: A New Paradigm for Performing Logic Synthesis
  • A New Voltage Binning Technique for Yield Improvement Based on Graph Theory
  • Ruijing Shen, Sheldon X.-D. Tan, Xue-Xin Liu
  • A Complete Power Estimation Methodology for DSP Blocks in FPGAs
  • Process Variation Aware DRAM Design Using Block Based Adaptive Body Biasing Algorithm
  • Design and Analysis of Emerging Devices
  • Device- and System-Level Performance Modeling for Graphene P-N Junction Logic
  • Quasi-Planar Tri-gate (QPT) Bulk CMOS Technology for Single-Port SRAM Application
  • A Body-Voltage-Sensing-Based Short Pulse Reading Circuit for Spin-Torque Transfer RAMs (STT-RAMs)
  • Interconnect analysis in spin-torque devices: performance modeling, optimal repeater insertion, and circuit-size limits
  • Analysis of Crosstalk Delay and Area for MWNT and Bundled SWNT in Global VLSI Interconnects
  • Variation-Aware Design Methodologies
  • Robust Metastability-based TRNG Design in Nanometer CMOS with Sub-Vdd Pre-charge and Hybrid Self-calibration
  • Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices
  • Error Mitigation in Digital Logic using a Feedback Equalization with Schmitt Trigger (FEST) Circuit
  • The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter
  • TDDB-Based Performance Variation of Combinational Logic in Deeply Scaled CMOS Technology
  • Critical Area Driven Dummy Fill Insertion to Improve Manufacturing Yield
  • Impact of Transistor Aging Effects on Sense Amplifier Reliability in Nano-Scale CMOS
  • A Highly Reliable SEU Hardened Latch and High Performance SEU Hardened Flip-Flop
  • A Scalable Curve-fit Model of the Substrate Coupling Resistances for IC Design
  • Efficient Reduction Techniques for Statistical Model Generation of Standard Cells
  • Efficient Electro-Thermal Co-analysis on CPU+GPU Heterogeneous Architecture
  • Dynamic Range Estimation for Systems with Control-flow Structures
  • Comparison of Variations in MOSFET versus CNFET in Gigascale Integrated Systems
  • Vertical Slit Field Effect Transistor in Ultra-Low Power Applications
  • Design and Optimization of Power Gating for DVFS Applications
  • An Area Efficient On-Chip Hybrid Voltage Regulator
  • Device and electromagnetic co-simulation of TSV: substrate noise study and compact modeling of a TSV in a matrix
  • A Case for 3D Stacked Analog Circuits in High-Speed Sensing Systems
  • A DyadicCluster method used for Nonlinear Placement
  • Clock Mesh Framework
  • Placement Aware Clock Gate Cloning and Redistribution Methodology
  • Impact of C-Elements in Asynchronous Circuits
  • A Top-Down Design Methodology using Virtual Platforms for Concept Development
  • Partitioning and Dynamic Mapping Evaluation for Energy Consumption Minimization on NoC-Based MPSoC
  • Ordinary Kriging Metamodel-Assisted Ant Colony Algorithm for Fast Analog Design Optimization
  • CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects
  • DRC-Free High Density Layout Exploration with Layout Morphing and Patterning Quality Assessment, with Application to SRAM
  • Hierarchical Power Network Synthesis for Multiple Power Domain Designs
  • Algorithmic Study on the Routing Reliability Problem
  • Robust SRAM Design
  • A 40-nm 256-Kb 0.6-V Operation Half-Select Resilient 8T SRAM with Sequential Writing Technique Enabling 367-mV VDDmin Reduction
  • Process Variation Tolerant 9T SRAM Bitcell Design
  • History and Variation Trained Cache (HVT-Cache) A Process Variation Aware and Fine Grain voltage Scalable Cache with Active Access History Monitoring
  • VAR-TX: A Variability-Aware SRAM Model for Predicting the Optimum Architecture to achieve Minimum Access-Time for Yield Enhancement in Nano-scaled CMOS
  • Bit Error Rate Estimation in SRAM Considering Temperature Fluctuation
  • 3D Effects on Package Co-Design
  • Chip-Package Power Delivery Network Resonance Analysis and Co-design Using Time and Frequency Domain Analysis Techniques
  • Maintaining Power Integrity by Damping the Cavity-Mode Anti-Resonances’ Peaks on a Power Plane by Particle Swarm Optimization
  • A Design Tradeoff Study with Monolithic 3D Integration
  • Cost-minimized Double Die DRAM Packaging for Ultra-High Performance DDR3 and DDR4 Multi-Rank Server DIMMs
  • Advanced Analysis and Characterization for Sub-Micron Design
  • Speed-path Analysis for Multi-path Failed Latches with Random Variation
  • HiSIM-RP: A Reverse-Profiling Based 1st Principle Compact MOSFET Model and Its Application to Variability Analysis of 90nm and 40nm CMOS
  • An Accurate Current Source Model for CMOS Based Combinational Logic Cell
  • Efficient Approaches to Overcome Non-Convexity Issues in Analog Design Automation
  • Optimization of Importance Sampling Monte Carlo using Consecutive Mean-shift Method and its Application to SRAM Dynamic Stability Analysis
  • Metamodel-Assisted Ultra-Fast Memetic Optimization of a PLL for WiMax and MMDS Applications
  • Power-Aware Design
  • 24% Power Reduction by Post-Fabrication Dual Supply Voltage Control of 64 Voltage Domains in VDDmin Limited Ultra Low Voltage Logic Circuits
  • Enhancing Efficiency and Robustness of a Photovoltaic Power System under Partial Shading
  • Comparison between power gating and DVFS from the view point of energy efficiency
  • Design of Low-Power, Scalable-Throughput Systems at Near/Sub Threshold Voltage
  • Analysis and Evaluation of Greedy Thread Swapping Based Dynamic Power Management for MPSoC Platforms
  • Efficient Leakage Power Saving by Sleep Depth Controlling for Multi-mode Power Gating
  • Circuit-Level Variability and Manufacturability
  • DDRO: A Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators
  • An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design
  • Process Mismatch Analysis based on Reduced-Order Models
  • Transistor Channel Decomposition for Structured Analog Layout, Manufacturability and Low-power Applications
  • Theory of Redundancy for Logic Circuits to Maximize Yield/Area
  • A Novel Sample Reuse Methodology for Fast Statistical Simulations with Applications to Manufacturing Variability
  • Verification and Silicon Debug
  • Monitoring and Timing Prediction in Early Analyzing and Checking Performance of Interconnection Networks at ESL
  • Automated Correction of Design Errors by Edge Redirection on High-Level Decision Diagrams
  • Assertion Clustering for Compacted Test Sequence Generation
  • Transaction-Based Post-Silicon Debug of Many-Core System-on-Chips
  • An Enhanced Debug-Aware Network Interface for Network-on-Chip
  • Challenges and Opportunities in New Technologies
  • Process Induced Mechanical Stress Aware Poly-Pitch Optimization for Enhanced Circuit Performance
  • Design Issues and Insights of Multi-Fin Bulk Silicon FinFETs
  • Self-Heating Effects in Gate-all-around Silicon Nanowire MOSFETs: Modeling and Analysis
  • Comparison of Electrical, Optical and Plasmonic On-Chip Interconnects Based on Delay and Energy Considerations
  • Design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices
  • Energy-Aware System Design
  • Learning Based DVFS for Simultaneous Temperature, Performance and Energy Management
  • Hot Peripheral Thermal Management to Mitigate Cache Temperature Variation
  • Power-Performance Yield Optimization for MPSoCs Using MILP
  • A Variation and Energy Aware ILP formulation for Task Scheduling in MPSoC
  • Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis

More info: International Symposium on Quality Electronic Design (ISQED)