CDNLive! User Conference in Silicon Valley Taking Place Next Week

Cadence Design Systems is hosting their annual CDNLive! User Conference in Silicon Valley next week. The user event features technical papers, keynote speakers, techtorials, networking opportunities, and a designer expo. CDNLive! brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems. CDNLive! Silicon Valley will take place at the DoubleTree Hotel, San Jose, California from March 13-14, 2012.

2012 CDNLive! Topics

  • In-Design DFM in Digital Implementation: Process Hotspot Repair at the 32/28nm Node Using Pattern Matching
  • A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP
  • GLOBALFOUNDRIES 28nm Analog and Mixed Signal Production Ready Flow
  • A Methodology for Concurrent Coverage-Driven Verification
  • Integrating 28nm DDR PHYs – Challenges and Considerations
  • SDS/System: General Presentation Overview
  • Flow and library validation on a 22nm SOI testchip
  • Quantifying the design impact of Double Patterning for the 20nm and 14nm technology nodes
  • IC 61 and EDI 10.1 Inter-Operability Flow, Features and Benefits
  • LDE Aware Design Flow Automation
  • Best Practice of Assertion-Based Verification
  • 3D Stacking of DRAM: Why Wide-IO is driving TSV
  • Easing the Concurrent Hardware and Software Development with Standards, Tools and Virtual Platforms
  • Functional Verification of Next Generation ICs with Next Generation Tools – Applying Palladium XP Simulation Acceleration to an Existing Specman Testbench Framework
  • Being Green – what Good design and ccopt (formerly Azuro) can do to reduce Power
  • Early Architecture Exploration using EDI
  • 20nm technology challenges on PDK development
  • Bypassing Bypass Logic Verification Trouble with Automation of Memory Wrapper Verification (Without UVM, VMM, or OVM)
  • Deployment of Advanced PCI Express Gen3 Controller IP in Networking and Storage Applications
  • Virtual Platforms: technology, application and experiences
  • Enabling a new paradigm of system-level debug productivity while maintaining full in circuit emulation performance
  • Mali-T604 Embedded General Purpose Computing for GPU implementation in CMOS32LP using Cadence Reference Methodology
  • Parasitic Extraction with QRC at 20nm
  • RNM Model Development and Application in Mixed-Signal SOC Verification
  • Circuit Prospector as a design reuse and modification tool
  • Customized Metric Driven Verification Planning and Management
  • Optimization of graphics data flow between Vivante’s high performance GPUs and Cadence’s DDR controller IP
  • Enterprise Configuration and Change Management of EDA ,Systems and Embedded Software assets with IBM Rational ClearCase and ClearQuest
  • Verification IP: growing from IP focus to full System design, system verification and testing
  • Implementation strategies for a high performance and low-power ARM Cortex-A15 processor: Methodology and tools usage best practices
  • How Conformal Constraint Designer enhanced our design flow
  • AMS Simulation of full duplex USB interface using strength modeled Connect Modules
  • Bring sign-off quality verification earlier in design flow with Virtuoso Integrated Physical Verification System
  • Design and Testbench Analysis: The SystemVerilog Challenge
  • PCIe post silicon validation
  • 200X acceleration of HW/SW integration and debug using a virtual A15 CPU sub-system and emulated RTL
  • SysML addressing EDA needs with IBM Rational Rhapsody
  • Improving Performance, Power and Area of a High Speed Dual-core ARM Cortex-A9 Processor with Clock Concurrent Optimization Technology
  • Comprehensive QRC/ETS solutions for 28nm Timing Signoff
  • Conformal Low Power – Complex Low Power Design Verification
  • AMS Reference Flows for Advanced TSMC CMOS Processes
  • Formal Verification of a QoS-based Arbiter
  • A Comprehensive Analysis and Verification Methodology for DDR3 Interfaces
  • Reference Flow for Early Software Development and Verification with ARM-based TLM Virtual Prototypes Including Connection to RTL
  • Challenges and solutions for implementing SoC designs in multi-FPGA prototyping systems
  • Mitigating Power Delivery Risk with Cadence Early Rail Analysis
  • Encounter Digital Implementation Floorplan Route Planning using Bus Guides
  • Low Power Implementation on Freescale Kinetis Family
  • From 6 Days to 6 Minutes: Accelerating Mixed-Signal Design Verification of a 45nm 2.4GHz Sigma-Delta Fractional-N Frequency Synthesizer Using Virtuoso AMS Designer Empowered by Automated Behavioral Modeling
  • Mechanism to allow easy writing of test cases in a SystemVerilog Verification environment, then auto-expand coverage of the test case
  • Accelerating the Methodology of PCB PDN Design and Analysis
  • Leveraging Virtual Platforms in Compute Sub-System Design
  • At-Speed Waveform Generation for Test Pattern Using Cadence Palladium
  • Hierarchical Synthesis Flow
  • 28nm digital methodology for dynamic RAM logic
  • Low-Power Format CPF in Analog and Mixed-Signal Simulation and Macro IP Verification
  • A User-Oriented SKILL Based Tool for Pre-Extraction Power-Grid Optimization, Targeting Accurate IR-Drop Analog Transient Simulations
  • Metric-Driven Verification: Going the Extra Mile
  • PCB and package co-design using 3D EM full wave simulation
  • Rapid IP-centric Virtual Prototype Development
  • Verifying Cache Coherent Designs, ACE and Interconnect Monitor
  • Parasitic Extraction Challenges for Display Technologies and its Applications
  • Cadence EDI System Interface and Implementation with IBM ASIC
  • SPEF/DSPF Parasitic Stitching in Post-Layout Analog and Mixed-Signal Simulation
  • Module Testing vs. Full Chip Verification – Methodology and Practical Tips
  • Why Doesn’t My Board Work?
  • Fast Processor Models for SystemC Virtual Platforms
  • No spin zone: Solid State Drives rock storage interfaces
  • Automated Strategy Selection in Conformal LEC for Easy Verification Closure
  • Distributed Parallel Test Architecture
  • An Efficient Phase-Locked Loop Noise Simulation Using APS and ViVA
  • An Evaluation of Fluid Guard Rings
  • UVM SDMAM technique for System Level SOC verification
  • IPC2581 — The 21st Century Approach to Transferring Design Data to Manufacturing
  • Multi chip Module (MCM) package design flow using Cadence SiP design tools and Agilent package analysis
  • System-C to Layout Metal-Only Engineering Change Orders: Fantasy or Reality?
  • High Performance, Interoperable Real Number Models for Mixed-Signal Verification
  • Electrical Variability due to Layout Dependent Effects: Analysis, Quantification, and Mitigation on 40 and 28nm SOC Designs
  • Verilog-AMS Verification of ADC Soft IP cores
  • Minimizing Schematic Migration with Autonomous Super Symbols
  • Techtorial: Low Power Failures – What not to Plan
  • Creating Apps for OrCAD Capture: Experiences, Tips, and Examples
  • Using Co-Design to Optimize System Interconnect Paths
  • Efficient enterprise deployment of verification computing platforms solving diverse verification
  • Substrate Noise Analysis and Wide Metal Extraction for Power MOS embedded LSIs
  • RC Bottom-up DFT insertion in a hierarchical Place-and-Route flow
  • Use-model schemes for AMS OSS/IRUN flow with multiple digital abstractions
  • PVS Double Patterning Technology for 20nm
  • Low-power Verification using UVM SystemVerilog
  • Improving IDF geometry definitions
  • Silicon-Package-Board Co-Design and Co-Analysis for a High Performance Multicore Chip
  • Why DisplayPort will be the next display choice of PC Vendors, OEMs and their verification challenges

More info: CDNLive! Silicon Valley