Cadence Design Systems announced a new RTL-to-GDSII flow. The latest release of the Cadence Encounter RTL-to-GDSII flow features GigaFlex technology, physical-aware synthesis, GigaOpt engine, and differentiated CCOpt technology. The updated flow is ideal for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. It enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today’s market requirements.
The new RTL-to-GDSII design, implementation and signoff flow was developed in close collaboration with leading IP and foundry vendors and Cadence customers. The new RTL-to-GDSII is enabled by Encounter RTL Compiler, Encounter Test, Encounter ECO Designer, Encounter Digital Implementation System, Clock Concurrent Optimization (CCOpt), Encounter Timing System, Encounter Power System, Cadence QRC Extraction, Cadence Physical Verification System, and design for manufacturing technologies.
New Cadence Encounter RTL-to-GDSII Flow Highlights
Encounter 20-nanometer Methodology
The flow’s 20nm methodology includes correct-by-construction double-patterning support, which covers capabilities from floorplanning, placement and routing to signoff timing, power and physical verification. This improves die area efficiency of 20nm double-patterning designs, and enables more efficient engineering change order (ECO) revisions.
New GigaOpt Engine
The new Encounter RTL-to-GDSII flow features the new GigaOpt engine, which uniquely integrates key physical-aware synthesis technology with physical optimization, enabling faster timing closure and better correlated results. It is a highly scalable optimization engine that supports designs featuring leading high-performance processors. By harnessing the power of multiple CPUs, the engine produces results much faster than traditional optimization engines.
The Cadence design flow includes new differentiated CCOpt technology that unifies clock tree synthesis with physical optimization, resulting in up to 10% improvement in design performance, and up to 30% reduction in clock tree power and area.
The new Cadence flow features GigaFlex technology. Designers can now achieve full-chip design prototyping goals in only 10% of the time required previously, enabling them to uncover potential issues earlier to produce the optimal design floorplan sooner. The GigaFlex technology enables concurrent top-and-block hierarchical design and implementation, reducing iterations and total design cycle time by an order of magnitude. In addition, automated functional ECO technologies accelerate pre- and post-mask ECO changes, which are reduced to hours or days through smart hierarchical design handling.
More info: Cadence Design Systems, Inc.