Tensilica Unveils ConnX BBE32UE Digital Signal Processor IP Core

Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW (28 nm HPL process). The ConnX BBE32UE is available now for early access customers. General product release is planned for the third quarter of 2012.

The ConnX BBE32UE DSP is built around a core vector pipeline made of 32 18bx18b MACs. The multipliers and associated adder and multiplexer trees enable operations such as Matrix computation, parallel complex multiple operations and signal filter structures. The results of these operations can be full precision or truncated/rounded/saturated and shifted to meet the needs of different algorithms and implementations. High precision is a key factor with ConnX BBE32UE and, as a result, more signed multiplication results can be accumulated without loss of precision, with fewer register spills and lower power.

ConnX BBE32UE DSP Core Features

  • High-performance, very low power DSP core with 32 simultaneous 18×18-bit MACs/cycle
  • DSP architecture and instruction set specifically optimized for wireless communications user equipment applications
  • Supports a variety of complex arithmetic operations and efficient matrix processing with SIMD acceleration
  • Wide vector processing pipeline with up to 16-way SIMD support and 3-issue VLIW for efficient parallel load/store and compute operations
  • Dual 320b wide vector register files supporting for 20b x 16 and 40b x 8 vector types
  • 256b load/store unit and 256b load unit
  • Based on the Xtensa LX platform with rich customization and extension capabilities
  • Extensible interfaces with customized FIFO, Port and Lookup interfaces
  • Support 2G, 3G, LTE and HSPA+ standards
  • Optional acceleration units available:
    • 16-way SIMD integer and fractional divide
    • 8-way SIMD reciprocal square root
    • De-spread (32-way), including Hadamard transforms
    • 3GPP soft bit demapping
    • LFSR generation
  • Optional support for non-aligned vector data load
  • Supported by Tensilica advanced compiler and development tool chain
  • DSP function and application specific function libraries

More info: Tensilica, Inc.