Synopsys Introduces Discovery Verification IP Family with VIPER Architecture

Synopsys introduced their Discovery Verification IP (VIP) family. Synopsys VIP is written entirely in SystemVerilog and is based on the new VIPER Architecture. It offers speeds and simplifies the verification of complex protocols and SoC designs. The Synopsys Discovery VIP family includes Protocol Analyzer, which is a unique prothonotary debug environment. Synopsys VIP is available for a variety of protocols, including USB 3.0, ARM AMBA AXI3, AXI4, ACE, HDMI, MIPI (CSI-2, DSI, HSI, etc.), Ethernet 40G/100G, PCI Express, SATA, and OCP.

Synopsys’Discovery Verification IP supports all major simulators and offers up to four times higher performance than other commercial VIP, as well as configuration, coverage and test-development capabilities to improve IP and SoC designers’ productivity.

Unlike other commercially available VIP, Discovery VIP is written entirely in SystemVerilog without any wrappers or methodology extensions around an original implementation in a different language. Discovery VIP is architected with native support for UVM (Universal Verification Methodology), VMM (Verification Methodology Manual) and OVM (Open Verification Methodology) without methodology-level interoperability wrappers or under-the-hood translations or remapping. Not only does this remove unnecessary performance overhead, but it also offers other uniquely inherent benefits. These benefits include portability across all major simulators and easy integration within SoC environments, as well as capabilities and features for VIP debug, coverage planning and management.

The Discovery VIP family is based on Synopsys’ new VIPER architecture, which has been engineered from the ground up for enhanced VIP performance, configurability, portability, debug, coverage and compliance management, and extensibility. The bulk of VIPER’s functionality and protocol correctness-checking comes from a layered protocol architecture implemented in SystemVerilog, using best practices for all methodologies, including UVM, VMM and OVM. All layers are visible, providing complete controllability of protocol verification. Verification engineers are able to work at the highest layer as required by their verification plans, yet are still able to inject errors at the lowest layer for self-checking requirements.

The VIPER architecture offers the ability to track protocol-centric simulation information to provide protocol-level analysis views with timelines synchronized to RTL waveforms and other views. This architecture can be fully configured to specified protocol configurations and includes several capabilities such as pruning of non-applicable run-time configurations from pre-defined sequences. The VIPER architecture is also highly extensible, accommodating additional capabilities unique to the device-under-test (DUT) such as error injection modes, coverage sampling, and other capabilities.

More info: Synopsys, Inc.