Mentor Graphics is expanding support for the Universal Verification Methodology with UVM Express and UVM Connect. UVM Express is one way to progressively adopt UVM methodology. UVM Connect provides standard TLM 1.0 and TLM 2.0 connectivity between models written in SystemC and UVM SystemVerilog. UVM Express and UVM Connect functionality is available now. They can be downloaded from the Mentor Verification Academy. Verification Academy modules on using UVM (UVM Express and UVM Advanced), training material and online documentation are also available.
UVM Express is a collection of techniques, coding styles and UVM usages that are designed to increase the productivity of functional verification. The techniques include raising the abstraction level of tests, writing tests using BFM function and task calls, adding functional coverage, and adding constrained-random stimulus generation.
UVM Express provides a way to build a testbench environment, a way to raise the abstraction level, a way to check the quality of tests and a way to think about writing tests. Each of the steps outlined for UVM Express is a reusable piece of verification infrastructure. These UVM Express steps are a way to progressively adopt a UVM methodology, while getting verification productivity and verification results at each step.
Using UVM Express is not a replacement for full UVM, but instead enables full UVM migration or co-existence at any time. UVM Express helps everyone, regardless of their experience level, to accelerate time to success.
UVM Connect is a new open-source UVM-based library that provides TLM1 and TLM2 connectivity and object passing between SystemC and SystemVerilog UVM models and components. UVM Connect enables engineers to easily develop integrated verification environments where they can take advantage of the strengths of each language to maximize verification productivity.
By facilitating cross-language communication via standard transaction level modeling (TLM) interfaces, UVM Connect enables the reuse of SystemC architectural models as reference models in SystemVerilog verification, and expands the inventory of Verification IP (VIP) by making it easier to integrate off-the-shelf VIP. It helps verification teams to maximize productivity in a mixed-language, mixed-tool environment by using either SystemC or SystemVerilog to implement key pieces of their testbench and provides direct access to UVM state and control flow from outside SystemVerilog.