DVCon 2012 Features Tutorials, Panels, Technical Sessions, and Keynote

This year’s Design and Verification Conference and Exhibition will take place next week, February 27th to March 1st, in San Jose, California. DVCon 2012 is a conference for functional design and verification. The event will focus on bringing information from the leading edge of technology, techniques, standards and methods. This year’s DVCon Expo will feature tutorials, panels, technical sessions and 34 exhibitors.

DVCon 2012 Tutorials, Panels, Technical Sessions, and Keynote

  • An Introduction to IEEE 1666-2011, the New SystemC Standard
  • UVM: Ready, Set, Deploy!
  • An Introduction to the Unified Coverage Interoperability Standard
  • Verification and Automation Improvement Using IP-XACT
  • Low-Power Techniques
  • UVM Techniques
  • SystemC and Beyond
  • Verification Benchmarking and Efficiency
  • Formal Techniques
  • Mixed-Signal Verification
  • The Resurgence of Chip Design
  • Verification and Debugging Tips
  • Getting to Coverage Closure
  • UVM in a Multi-Platform World
  • UVM Stimulus Generation
  • Verification Case Studies
  • SystemVerilog Tips and Techniques
  • Systemic Collaboration: Principles for Success in IC Design
  • Build or Buy: Which is the Best Practice for Hardware-Assisted Verification?
  • Using Apps to Take Formal Analysis Mainstream
  • Design and Verification of Platform-Based, Multi-Core SoCs
  • Leveraging Formal Verification Throughout the Entire Design Cycle
  • New Levels of Verification IP Productivity for SOC Verification

More info: DVCon