Cadence Design Systems introduced 40/100 Gigabit Ethernet media access controller and physical coding sub-layer IP cores. The new Cadence 40/100 GbE MAC and PCS IP cores speed the deployment of SoCs for networking and high-performance computing. The design IP, including MAC and PCS, as well VIP, emulation and virtual prototyping support, are available now.
The new 40/100 Gigabit Ethernet media access controller and physical coding sub-layer IP cores support the latest version of the IEEE 802.3ba-2010 Ethernet specification and sub-specifications including Energy Efficient Ethernet for power savings during idle time. The IP includes a host of configurable features such as Ethernet address match logic and frame- and priority-based flow control mechanisms for application-based customization of traffic control.
The Cadence 40/100 GbE MAC and PCS IP cores include a programmable inter-frame gap that feature that enables precise packet flow control to avoid equipment overload. In addition, the new IP provides comprehensive monitoring features. These include error/status word for each frame that is transmitted and received, remote monitoring (RMON) and management information base (MIB) support. The 40/100 GbE MAC IP supports Gigabit media independent interfaces (XLGMII and CGMII) for connection to the attached PHY layer device, whereas the 40/100 GbE PCS IP supports integration with four/ten 10 Gigabit SerDes.
More info: Cadence Design Systems, Inc.