Synopsys rolled out DesignWare Embedded Memory and Logic Library IP for TSMC’s 28 nanometer high-performance and high-performance for mobile process technologies. The DesignWare Embedded Memories and Logic Libraries for TSMC’s 28HP and 28HPM processes are part of the DesignWare Duet Package, which includes SRAMs, ROMs, standard cells, Power Optimization Kits (POKs) and optional overdrive/low voltage PVTs. The Duet Package for TSMC’s 28HP and 28HPM processes is available now.
The Synopsys DesignWare Embedded Memories and Logic Libraries are designed to deliver high performance with low leakage and active power. The new extension gives engineers the ability to optimize their entire system-on-chip (SoC) design for speed and energy efficiency. In combination with the embedded test and repair technology of the DesignWare STAR Memory System, Synopsys’ embedded memories and standard cell libraries offer designers an advanced, comprehensive IP solution for creating high-performance, low-power 28-nm SoCs with reduced test and manufacturing costs.
Synopsys’ DesignWare 28nm Logic Libraries take advantage of multiple threshold variants and gate length bias combinations to deliver optimal performance and power results for a wide variety of SoC applications. The libraries offer multiple, synthesis-friendly cell sets and router-friendly standard cell library architectures designed for multi-GHz performance with minimal die area and high manufacturing yield. Power Optimization Kits (POKs) provide designers with advanced power management capabilities supported by leading low-power design flows, including shut-down, multi-voltage and dynamic voltage frequency scaling (DVFS).
More info: Synopsys, Inc.