2012 Pan Pacific Microelectronics Symposium to Take Place Hawaii

Here is a great event for engineers: the Pan Pacific Microelectronics Symposium in Kauai, Hawaii. With this conference, you can learn something and take a nice vacation too. The event promotes international technical interchange and provides a premier forum for networking among microelectronics professionals and business leaders throughout the world. The Pan Pacific Microelectronics Symposium will take place next week, February 14-16, 2012.

Pan Pacific Microelectronics Symposium Topics

  • Industry-University Collaboration and Advances in Lead-Free Solder Technology
  • Stability of Cu6Sn5 in the Formation and Performance of Lead-free Solder Joints
  • Thin Palladium Layers as an Effective Cost Saving Strategy in Electronics Applications
  • Coffin-Manson Formula for Sn/3.0Ag/0.5Cu Solder Joints
  • Tin-Copper-Nickel-Germanium – A Case Study in Lead-Free Implementation
  • New 3D Packaging Approach for Next Generation High Performance DRAM
  • 3D IC Technology Perspectives in Taiwan
  • 3D Integration Packaging by Organic and Glass Materials
  • 3D Integration – A Promising Approach for Smart Systems Integration
  • 3D Heterogeneous Integration: 3D ICs with TSV vs. 3D Interposer with TPV
  • IPC International Technology Roadmap for Electronic Interconnectors
  • TSVs – A Defining Technology for 3D Integration
  • JISSO Electronics Technology Roadmap Through 2020
  • 2011 iNEMI Technology Roadmap and Its Place in Fulfilling the iNEMI Mission
  • Technology Roadmaps and their Importance to Product Competitiveness
  • Roadmapping Risks and Returns
  • EU Electronics Research and Development Direction; Highlights of Framework 7 and Expectations for Framework 8
  • Investigation on Root Cause for Via with Solder Bubble
  • Evaluation of Molded Underfill Packages Using Acoustic Micro Imaging
  • Investigation on Pad Crater Failure of BGA Solder Joints
  • Investigation of Factors That Influence Creep Corrosion
  • Solder Paste Printing and Solder Paste Inspection Optimization Strategy for the PCBA SMT Process
  • Dielectrics for the Embedding of Active and Passive Devices
  • Methods of Micro Ball Bumping for Wafer Level and 3D Applications Using Solder Sphere Transfer and Solder Jetting
  • Copper Pillar Bump Process Characterization on 300mm Wafers
  • Printed Electronics — The Evolution of a Once and Future Technology
  • Evaluation of the Neville Distribution for Studying the Brittle Failure Mode in Microelectronics Drop Testing Studies
  • Critical Parameter Leads to Failure of Lead-Free under Thermal Cycling
  • Stress Analysis of Multilayered Printed Circuit Board Under Mechanical Loading
  • PCB Dynamic Co-Planarity at Lead-Free SMT Temperatures (iNEMI)
  • Developing the iNEMI Research Plan
  • Plenty of Room at the Bottom; Nanomaterials Emerge as an Electronics Powerhouse
  • Roadmaps for ESD (Electrostatic Discharge) – True Prospects of Just Interests of the Industrial Enterprises
  • Silicon and Packaging Technology Trends in High Performance Networking
  • Pushing the Limits of Lead-Free Soldering
  • Fluid Flow Kinetics for Encapsulation Processes in Small and Anisotropic Electronic Packages
  • Towards Large Area Roll-to-Roll (R2R) Flexible Multilayer Electronics
  • Electroless Plating Process on Glass Substrate
  • Automated Precision Assembly High Volume HB LEDs
  • SMART Commercialization Center for Microsystems – A New Model to Drive Industry Development
  • Silver-Polyaniline-Epoxy Electrical Conductive Adhesives – A Percolation Threshold Analysis
  • Recent Advances in Anisotropic Conductive Adhesives (ACAs) Technology
  • Low Temperature Processing Conductive Adhesives for High Temperature Applications
  • Sustainable Electronics
  • Material Selection and Parameter Optimization for Reliable TMV PoP Assembly
  • TSV Technology – Updated Status
  • Equipment and Process Solutions for Low Cost High Volume Manufacturing of 3D Integrated Devices
  • Technology Alternatives Towards Low-Cost and High-Speed Interconnect Manufacturing
  • 3D Contactless Capacitive Coupled Interconnection Circuit Design
  • Silicon Interposer Design for a 12X10 Gb/s Electro-Optical Engine

More info: Pan Pacific Microelectronics Symposium