Cadence, Samsung Foundry Develop DFM Flows for 32nm, 28nm, 20nm Chip Design
Cadence Design Systems and Samsung Foundry teamed together to create a design-for-manufacturing infrastructure to produce complex chips. Cadence worked closely with Samsung Foundry to integrate their robust DFM suite. The resulting flows and underlying infrastructure provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.
Cadence Design Systems and Samsung Foundry have developed in-design and signoff DFM flows to deal with physical signoff and electrical variability optimization for 32-, 28- and 20-nanometer SoC designs. The new flows address both random and systematic yield issues, and provide engineers with a proven foundry option for advanced-node designs built on the Cadence Encounter digital and Cadence Virtuoso custom/analog implementation solutions.
The Cadence in-design approach to Silicon Realization moves traditional DFM steps into the implementation stage of digital and custom chip design. This unique approach is aimed at boosting productivity, predictability and profitability while reducing risk. The DFM flows developed at Samsung Foundry leverage multiple groundbreaking technologies, including Cadence Pattern Classification and Search, Cadence CMP Predictor, Cadence Litho Physical Analyzer and Cadence Yield Analyzer and Optimizer.
With the new infrastructure optimized for advanced nodes, Samsung Foundry is able to use the hierarchical design approach and pattern matching to perform effective and accurate systematic failure analysis. In addition, the Cadence production-proven in-design DFM prevention and optimization in Cadence Encounter digital and Cadence Virtuoso custom/analog implementation solutions enables first-time-correct silicon.
The Cadence pattern classification technology enables Samsung Foundry to classify the yield detractor patterns into easily usable pattern libraries. The infrastructure helps designers to leverage the in-design and signoff pattern matching with automated fixing flows in Encounter and Virtuoso. The development of a chip-based CMP analysis flow to enable early convergence of topography yield issues in advanced digital and custom designs is another development of the Cadence-Samsung collaboration.
More info: Cadence Design Systems, Inc.
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