Apache Design, Inc. is sponsoring two Chip-Package-System (CPS) workshops at DesignCon 2012. The two in-depth technical workshops will provide designers with an open forum for exchanging the latest ideas and information on the most current technologies. In the interactive workshops, leading semiconductor companies and system houses will share perspectives and best practices on chip and package modeling, and system-level verification for signal integrity, power integrity, electromagnetic interference and thermal. The workshops are free. However, seating is limited and registration is required.
At DesignCon, Apache Design will also showcase advanced low-power solutions for chip-level power analysis, optimization, and sign-off, as well as comprehensive methodologies for chip-package-system convergence. Apache, a subsidiary of ANSYS, will demonstrate how their multi-physics engineering software portfolios enable innovative simulation-driven IC and electronic system development for power-efficient, high-performance and noise-immune electronic products.
CPS Methodology for Cost-Down and/or Reliability (Session SS-200)
February 1, from 10:15 a.m. to 12:15 p.m. in Ballroom H
This session features speakers from Intel and Cisco who will discuss how the performance and cost demands of today’s chip designs require a comprehensive chip-package-system approach to analysis. These industry experts will share their insights and expertise with case studies and real design examples for CPS convergence, and will discuss various aspects of analysis methodologies and technologies in terms of modeling, extraction and simulation.
CPS for 3D-IC and Power-Thermal-Mechanical-Electrical Applications (Session SS-201)
February 1, from 2:00 p.m. to 4:00 p.m. in Ballroom H
This session includes speakers from Micron, LSI and Xilinx who will focus on the challenges created by 3D stacked die and 2.5D Silicon Interposer with TSV chip designs. These leading technologists will examine modeling and simulation challenges in 3D-IC design and explore methodologies for power delivery network analysis, chip-to-chip communication, and thermal integrity using real case studies.