Webinar: Understanding the Basics of Parallel Wafer Level Reliability
Keithley Instruments, Inc. will host a one-hour webinar about parallel wafer level reliability testing. The free webcast will take place Thursday on January 26, 2012. It will be broadcast twice: 15:00 CET (9:00 AM EST) and 2:00 PM EST. The title of the online seminar is Understanding the Basics of Parallel Wafer Level Reliability. The webinar is ideal for engineers who are new to semiconductor reliability testing, test engineers who need to accelerate WLR testing, and QRA lab managers.
The webinar will discuss how to estimate the speed and throughput impact of parallel wafer level reliability (WLR) testing on traditional reliability structures and how to assess traditional test structures for use in a parallel test system. The web-based seminar will also address the source of measurement errors that impact WLR measurements, as well as typical configuration, measurement, and optimization techniques.
Parallel wafer level reliability testing provides a tool to accelerate throughput significantly by providing statistically significant samples sooner. New parallel WLR test solutions offer throughput benefits for both traditional and advanced WLR measurements. WLR tests are commonly performed throughout the semiconductor lifecycle — from technology development and process integration to process reliability monitoring. The speed and accuracy of these tests impact the time to market for new device designs. This seminar examines the benefits and tradeoffs associated with parallel test solutions for WLR.
The webcast will be presented by Dave Rose. He is a senior staff applications engineer at Keithley Instruments, Inc. in Cleveland, Ohio, which is part of the Tektronix test and measurement portfolio. Rose joined Keithley in 1987 and has spent roughly half of his career in design engineering and the other half in applications engineering.
Register: Understanding the Basics of Parallel Wafer Level Reliability (WLR)
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