Cadence Memory Controller and PHY IP Supports ONFI 3

Cadence Design Systems expanded its Flash IP offering to include support for the Open NAND Flash Interface (ONFI) 3.0 specification. According to Cadence, it is the first company to provide a combined ONFI 3 controller and PHY IP solution. The enhanced Flash IP streamlines SoC and system design while ensuring an optimized ONFI 3 implementation for maximum performance. The Cadence ONFI 3 memory controller and PHY IP are available now. The EDA company is also offering supporting verification IP (VIP) and memory models to ensure successful implementation.

The Cadence controller and PHY IP implement advanced capabilities of the ONFI 3 standard including chip-enable interleaving, which results in significantly improved system performance when dealing with multiple flash devices. As a result, the IP can deliver up to 95% of a NAND device’s theoretical maximum throughput. Cadence implements highly configurable error correction techniques to improve performance even more and deliver enterprise class reliability. Delivering advanced configurability, low-power capabilities and support for system boot from NAND, the Cadence solution is scalable from mobile applications to the data center.

The Cadence ONFI 3 Flash and controller IP is backward-compatible with existing ONFI and Toggle standards. The existing Cadence IP offering supports the ONFI 1, ONFI 2, Toggle 1 and Toggle 2 specifications, and also provides asynchronous device support.

The ONFI 3 specification simplifies the design of high-performance computing platforms (such as solid state drives and enterprise storage solutions) and consumer devices (such as tablets and smartphones that integrate NAND Flash memory). The new specification defines speeds of up to 400 mega-transfers per second.

More info: Cadence Design Systems