Mentor Graphics introduced a set of protocol transactors for use with the Veloce hardware emulation platform. The Veloce transactors help engineers to stress-test a DUT that includes one or more protocol interfaces on the SoC at orders of magnitude faster than simulation. The protocol transactors can be used with both transaction-based acceleration and traditional In-Circuit (ICE) modes of operation. The Veloce transactors is available now for deployment.
Mentor Graphics’ protocol transactors are easy and convenient to use. They reduce overall testbench development time and complete more verification with less effort. Veloce transactors can accelerate verification IP (VIP) up to 10,000 times the speed of pure software simulation.
Veloce transactors enable the use of stimuli generated by modern simulation testbenches, including SystemVerilog/OVM and UVM, SystemC, and ‘C’- based environments, and apply them to the design-under-test (DUT) running in the Veloce hardware. The connection between the testbench and the Veloce transactors are at a transaction-level, rather than signal interface. This results in a high level of performance.
The Mentor Veloce protocol transactors provide protocol solutions for ARM’s AMBA AXI, AHB, and APB standards, Universal Serial Bus (USB), PCI Express, Serial Attached SCSI (SAS), SPI, I2C, and audio standards, including I2S. The ability to use the same testbench in both simulation and emulation leverages testbench development across the two platforms and accelerates design regression testing by hundreds of times over simulation.
The Veloce transactors can be used with both transaction-based acceleration and traditional In-Circuit (ICE) modes of operation. Engineers can develop testbenches in one of several supported high-level verification (HVL) environments, and then seamlessly interchange between simulation and acceleration. This creates an effective and productive environment to develop new, leading-edge SoCs and accelerates delivery schedules.
More info: Mentor Graphics