SpringSoft introduced the Laker Blitz chip-level layout editor. The new software tool is optimized for speed and productivity during the final steps of the physical design process. It streamlines tapeout-to-manufacturing operations by enabling high-speed viewing and editing of chip-level layouts. Laker Blitz is ideal for designs with large data sets, such as advanced-node system-on-chip (SoC) implementations and large memory chips that are widely used in consumer electronics. The new SpringSoft software is available now for production use.
Laker Blitz uses new database technology for the rapid import, editing and export of massive GDSII data files, which are typically tens of gigabytes or more in size for current generation chips. This enables designers to easily load, view and manipulate chip-level layouts with access to the complete layout hierarchy. Engineers can perform cell, window or full-chip DRCs, and then find and fix violations without leaving the Laker Blitz environment. The tool also features net highlighting commands to trace critical nets. Laker Blitz is built on the same technology platform deployed by SpringSoft’s Laker Custom Layout Automation System.
Laker Blitz Highlights
- Reduces final tapeout-to-manufacturing cycles
- Ensures high quality designs with fast full-chip debug
- Diminishes the cost of IP merging
- Loads and views huge GDSII files 5 to 20 times faster than conventional layout editors
- Manipulates layout data for IP merging and SoC assembly applications
- Runs cell, window or full-chip DRC reviews and makes layout corrections in single environment
- Built-in net highlighting capabilities to rapidly trace critical nets for full-chip debug
- Automated data manipulation with extensive library of Laker Tcl extensions
- Integrated DRC with all top tier sign-off tools, including Calibre and IC Validator
- Laker APIs for internal chip finishing and third-party tool integration
More info: SpringSoft