Mentor Questa and Veloce Verification Tools Support ARM Cortex A7, A15 MPCore

According to Mentor Graphics, their Questa and Veloce functional verification platforms have expanded their support for designs based on the latest ARM Cortex processors and AMBA bus interfaces. The Questa Codelink with support for ARM Cortex A7, Cortex A15, other Cortex A-family, Cortex R-family, and Cortex M-family processors and Questa Verification IP with support for AMBA4 ACE are available now.

The expanded support helps both hardware and software engineers to fully verify multi-core ARM-based designs seamlessly across the Questa verification and Veloce emulation platforms. Questa and Veloce functional verification platforms are optimized to support multi-core hardware and software verification for next generation SoCs that leverage ARM’s big.LITTLE processing.

The Mentor library of accelerated Instruction Set Simulation (ISS) models now includes support for ARM’s newest Cortex A7 MPCore and Cortex A15 MPCore products. The Questa and Veloce verification platforms with the Questa Codelink product’s DVR-style of simulation/emulation playback for debugging can now be used to verify multi-core SoC designs based on ARM’s new processors.

Engineers can combine the RTL processor models with the ISS processor models, which can be hot-swapped on-the-fly during simulation. As a result, engineers can realize the benefits of accelerated simulation, without sacrificing accuracy for debugging. Because these models are portable to the Veloce emulation platform, software and hardware can be verified at faster speeds, all while enabling off-line debugging, leaving high-in-demand emulators to run even more regression tests.

Mentor Graphics has also expanded its library of verification IP (VIP) with the addition of AMBA 4 ACE support to Questa Verification IP. The ACE protocol adds hardware support for cache coherency bringing benefits in both power and performance. Mentor Graphics leveraged OVM and UVM, AMBA and cache-coherent, multi-processor system verification to create a comprehensive verification solution for ACE. Engineers can now completely verify and integrate IP supporting ACE quickly and with reduced cost with the comprehensive test, coverage, check and debug capabilities built into the Questa VIP.

More info: Mentor Graphics