EnSilica eSi-RISC Development Suite, Version 2.5

EnSilica rolled out version 2.5 of their eSi-RISC Development Suite. The eSi-RISC Development Suite v2.5 includes a host of new features and capabilities to enable their eSi-RISC processor family to be easily evaluated and quickly deployed. eSi-RISC Development Suite v2.5 features new capabilities for multicore support, improved compiler performance and ultra low-power applications support.

EnSilica eSi-RISC Development Suite, version 2.5

eSi-RISC Development Suite v2.5 Features

  • New capabilities for multicore systems support
  • Enhanced compiler performance
  • Support for ultra low-power applications
  • Offers JTAG debug and control over all processors in the JTAG chain
  • Optional load locked and store conditional instructions
  • Link Time Optimization (LTO) support
  • Scope of inter-procedural optimizations encompass the whole program — resulting in improved code density
  • Optimizing C/C++ compiler upgraded to GNU GCC version 4.6.1
  • Improved clock gating and operand isolation optimization in the RTL — 15% power reduction
  • New peripherals: AMBA AHB compatible static memory interface for external Flash and SRAM memory, AMBA AHB DMA Engine, AMBA APB I2C Slave and AMBA APB Smart Card interface supporting ISO-7816 standard
  • Support for Linux via the latest port of the GCC, GDB Debugger and GNU binary tools
  • New software examples and documentation to speed up evaluation and development
  • New application examples include a port of FreeRTOS, LwIP TCP/IP Stack, web server, and SPI Memory and CFI Flash programmer

More info: EnSilica