Cadence Design Systems and TSMC teamed together on a library characterization reference kit. The Cadence Library Characterizer (Altos Liberate) reference kit for TSMC’s standard cell libraries is now available to TSMC customers for download on TSMC-Online. As a result, TSMC customers can now leverage the same technology used in-house at TSMC with the same setup and constraints, helping them address the specific design challenges created through changes to their standard cell libraries.
Shrinking process geometries increase process variations and make creation of accurate noise, power and timing models for foundation IP very complex given smaller time-to-market windows. The combination of TSMC’s Library Characterization Reference Kit and the Cadence Library Characterizer enables engineers to speed the overall design schedule.
The reference kit, along with the Cadence Library Characterizer technology, help designers to re-characterize the standard cell libraries in-house, on their own schedule with the same characterization technology and setup used internally at TSMC, delivering better consistency.
The Cadence Library Characterizer technology enables re-characterization across process changes and additions to the IP library. It produces ultra-fast and accurate characterization of memory, standard cell libraries and other foundation IP, and generates required models for SoC implementation. TSMC has made Cadence Library Characterizer scripts for standard cell libraries available for 40- and 28-nanometer process nodes.