Mentor Graphics will conduct a technical seminar about the challenges of design and functional verification for complex multi-core SoC designs. The event, Design and Verification in the SoC Era, features keynote sessions delivered by John Goodenough (ARM) and Harry Foster (Mentor Graphics). It will take place on October 18, 2011 in San Jose, California. The Mentor Graphics seminar will run from 9am to 3pm Pacific time.
Design and Verification Seminar Sessions
Multicore ESL Design and Virtual Prototyping
New multi-core architectures offer higher performance but introduce new design challenges. Such architectures with complex hardware / software interaction require new methods to efficiently port, integrate, and tune firmware, operating system and application software against the hardware design. This session will cover Vista ESL Design and Virtual Prototyping unique solution that addresses power and performance tradeoffs, and enables fast and efficient software validation, debug, analysis and optimization against early model of the target hardware.
Multicore ESL verification refinement to RTL
Complex electronic systems with large embedded software running on Multi-core are becoming the greatest challenge in design verification. Mentor ESL-to-RTL flow has recently evolved to address this goal in a methodical, scalable and efficient way that brings together the hardware, software, and system-level disciplines. This session will describe how to validate hardware and software on a Virtual Prototyping platform at the ESL, and how to migrate to block and subsystem RTL verification in the context of the system, facilitating ESL model and platform reuse.
Accelerating Functional Verification from ESL to UVM
Hardware emulation spans the functional verification landscape from architectural exploration to block-level verification to full SoC HW/SW validation with complex peripherals. This session presents specific examples which detail the value emulation delivers at each phase of the functional verification process.
Intelligent Testbench Automation Accelerates Time to Coverage Closure
Achieving coverage closure is one of the most important, yet difficult challenges faced by verification engineers. The emergence of Intelligent Testbench Automation (“iTBA”) enables verification teams to achieve their coverage goals 10X to 100X faster than before. This session introduces iTBA, and shows how this new breakthrough can help you realize an order of magnitude gain in verification productivity. It will also highlight a real-life example of a verification team that accelerated its own functional verification process with Intelligent Testbench Automation, and now verifies more functionality in even less time.
Focusing, Automating and Accelerating Coverage Closure with a Plan
Verification is a dynamic process with the design specification, design implementation and the verification plan changing over the duration of the project. It can take a lot of effort to keep things in sync and ensure that documents do not get stale or, worse still, features and testing fall between the cracks. This session will show attendees how to apply Verification Planning techniques in process, tools and data management with Questa Verification Management and ReqTracer tools in order to accelerate their coverage closure and efficiently keep their plan in sync with changing requirements.
Understanding Coverage Holes – Design Bug, Test Limitation, or Don’t Care?
Engineers need to analyze the results to understand where the coverage holes are, and for each one, why it is there. This session will review the analysis of coverage results to identify and respond to coverage holes appropriately. Along the way we’ll show how static analysis tools such as Questa CDC and Questa Formal can be used to help identify and address coverage holes.
Modeling Registers with UVM
Modeling the hundreds or thousands of registers in your design is critical to your verification efforts. The UVM includes a Register Modeling facility that enables you to create a shadow copy of your hardware registers in your testbench to ensure the correct functionality and coverage of your registers. When paired with Certe Register Assistant, you can automatically generate your UVM register code, and associated built-in tests, from a register specification.
Integrating VIP Into Your Verification Environment
Modeling interface protocols is essential in ensuring that your DUT will operate correctly in your system. Questa VIP provides a pre-packaged, pre-verified, library of UVM verification components to model popular protocols as part of your UVM environment. This session will show you how to incorporate QVIP into your UVM environment and take advantage of the power and flexibility of QVIP.
Take the Fast-track to UVM Adoption
UVM holds many promises for advanced and reusable testbenches, but getting the whole team or company to adopt UVM can be a challenge. This session will discuss tools, techniques and resources that can rapidly get everyone to take on UVM and become productive quickly. The session will cover capturing and reusing UVM knowledge, correct-by-construction creation, analysis for understanding, build management for consistency, register package generation, effective design reviews, interactive debug, online up-to-the-minute methodology guidelines, expert advice/forums for help and training.