Webinar: Automating UVM to Tackle Insidious HW/SW Bugs

Duolog Technologies and Cadence Design Systems are hosting a webinar on automated UVM solutions to common hardware/software integration problems. The one-hour webcast is ideal for design and methodology engineers/managers who have encountered misalignment and synchronization errors in the HW/SW interface and wish to eliminate them in the future. The title of the event is Automating UVM to Tackle Insidious HW/SW Bugs. It will take place Tuesday, October 11th at 9:00am PDT (5:00 pm BST).

The webcast will include an interactive demonstration of a complete design and verification environment implemented using the Duolog Socrates and Cadence Incisive Enterprise Simulator products. The demonstration will illustrate how subtle bugs caused by miscommunication at the HW/SW and testbench/DUT interfaces can affect the quality of the system and produce alarming results. The webinar will demonstrate how an effective combination of advanced verification methodologies such as UVM and formal register management techniques can eliminate these bugs from the HW/SW integration process.

The webinar will also identify common problems associated with the integration of HW and SW and provides automated solutions to them. All HW/SW systems require multiple teams to agree on interface communications, however, subtle bugs due to miscommunication at the interface can infect the quality of the system especially where false-positive results occur. A combination of advanced verification methodologies such as UVM with formal register management techniques will be shown to eliminate this entire category of bugs from the process.

More info: Automating UVM to Tackle Insidious HW/SW Bugs Webinar Registration