ARM and Mentor Graphics Test Flow for ARM-based Designs

Mentor Graphics and ARM teamed together on a reference flow for manufacturing test of ARM processor-based designs. The reference flow features documentation, seamless interfaces, and scripts for accelerating the development of a complete test solution for ARM IP based on the Mentor Graphics Tessent test tools. The test flow is optimized for high test quality, lower test cost and shortened design-for-test development schedules.

The ARM-Mentor solution supports comprehensive testing of ARM cores and logic, and embedded memories used in customer SoCs. The test flow features the Mentor scan-based design-for-test and automatic test pattern generation (ATPG) tools with embedded compression. It also includes memory BIST with self-repair technologies. The reference flow defines all steps necessary for incorporating and verifying all test compression and memory BIST IP. It also generates all necessary test patterns. In addition, default scripting and configuration files make the automation flow even simpler.

System-on-chips include hundreds of memory subsystems that consist of different types of individual SRAMs, including single- and dual-port SRAM, register files and ROMs. Within each subsystem, the memories may range from high-speed SRAMs operating at higher voltages to power-optimized SRAMs operating at reduced voltage. All such memories have different test and/or repair requirements, depending on the size of the individual memory instances, total SoC memory size, process defect level and maturity. The Tessent solution is an automated memory test and repair solution with 100% accurate logical-to-physical mapping of ARM Artisan memories.

In addition to the many memory SoC subsystems, some of the memories are further embedded within processor cores which have been custom tailored to achieve the highest performance and lowest power in the smallest footprint. The additional complexity added by the need for proper test — and in some cases, repair of the memories contained in these optimized cores — mandates a test and repair solution that achieves the highest yield with minimal impact on SoC performance, power, footprint or cost. The ARM-Mentor solution feature Tessent support for the ARM MBIST core interface, which provides one or more interfaces for each embedded core, enabling full testing of every memory within each core with minimum impact on core power, performance or area.

More info: Mentor Graphics | ARM